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AssigneeCadence Design Systems, Inc.
InventorsWei-Jin Dai, Kit-Lam Cheong, Hsi-Chuan Chen, Wei-Lun Kao
Estimating the term…
An integrated circuit (IC) layout system initially modifies a netlist describing an IC as a hierarchy of circuit modules to combine clusters of cells forming selected modules so that they form a smaller number of larger cells. This reduces the number of cells forming the IC, thereby reducing the time the system needs to generate an IC layout. The system then generates a trial layout of the IC described by the modified netlist. Based on the shape and position of the area each module occupies in the trial layout, the system estimates the shape and position of a substrate area each module would require in a layout where module areas did not overlap. The system then divides the IC design into several partitions, each including separate set of the modules forming the IC, and creates a partition plan allocating substrate space to each partition based on the estimated space requirement of each module assigned to that partition. The system also creates a timing budget allocating signal path timing constraints among the partitions based on an timing analysis of signal paths delays in the trial layout. Thereafter the system independently lays out each IC partition so that it satisfies that partition's spatial and timing constraints as indicated by the partition plan and timing budget. The partition layouts are then assembled to form a complete IC layout.
A method for an automated placement and routing (P&R) tool for designing a layout on a constrained area of a semiconductor substrate of an integrated circuit (IC) described by a first netlist as interconnected cells organized into a hierarchy of circuit modules, wherein the cells form signal paths subject to signal path delay constraints, wherein the P&R tool includes a cell library containing a description of each cell of the IC, and wherein the first netlist identifies each cell by reference to its description in the cell library, the method comprising the steps of:
A method for an automated placement and routing (P&R) tool for converting a first netlist describing an integrated circuit (IC) into a second netlist describing the same IC, wherein the first and second netlists each describe the IC as interconnected cells organized into a hierarchy of circuit modules, wherein the P&R tool includes a cell library containing a description of each cell of the IC described by the first netlist, and wherein the first netlist identifies each cell of the IC by reference to its description in the cell library, the method comprising the steps of:
Computer readable media containing program instructions for converting a computer executing the program instructions into an automated placement and routing (P&R) tool for designing a layout on a constrained area of a semiconductor substrate of an integrated circuit (IC) described by a first netlist as interconnected cells organized into a hierarchy of circuit modules, wherein the cells form signal paths subject to signal path delay constraints, wherein the P&R tool includes a cell library containing a description of each cell of the IC, and wherein the first netlist identifies each cell by reference to its description in the cell library, the computer readable media comprising:
Computer readable media containing program instructions for converting a computer executing the program instructions into an automated placement and routing (P&R) tool for converting a first netlist describing an integrated circuit (IC) into a second netlist describing the same IC, wherein the first and second netlists each describe the IC as interconnected cells organized into a hierarchy of circuit modules, wherein the P&R tool includes a cell library containing a description of each cell of the IC described by the first netlist, and wherein the first netlist identifies each cell of the IC by reference to its description in the cell library, the computer readable media comprising:
Dependencies are inferred from the claim text.