Method and system for progressive clock tree or mesh construction concurrently with physical design

A method for clock tree generation in an integrated circuit design, said method comprising the steps of:

• (a) distributing latches among a first set of bins, wherein said first set of bins corresponds to a first level of said integrated circuit design;
• (b) performing topology selection between said first set of bins and a root for a first clock tree;
• (c) discarding all of said first clock tree outside of said first level;
• and
• (d) constructing clock tree segments for bins in each level of said integrated circuit design outside of said first level, wherein a clock tree for said integrated circuit design includes a clock tree segment associated with each level in said integrated circuit design, including a segment of said first clock tree from said first set of bins.

One or more computer readable storage devices having computer readable code embodied on said one or more computer readable storage devices, said computer readable code for programming one or more computers to perform a method for constructing a clock tree in an integrated circuit design, said method comprising the steps of:

• (a) distributing latches among a first set of bins, wherein said first set of bins corresponds to a first level of said integrated circuit design;
• (b) performing topology selection between said first set of bins and a root for a first clock tree;
• (c) discarding at least a portion of said first clock tree outside of said first level;
• and
• (d) performing topology selection between a second set of bins and a root for a second clock tree, wherein:
• said second set of bins corresponds to a second level of said integrated circuit design,
• said step (d) is based at least in part on said first clock tree, and
• said clock tree includes a portion of said first clock tree from said first set of bins and a portion of said second clock tree from said second set of bins.

One or more computer readable storage devices having computer readable code embodied on said one or more computer readable storage devices, said computer readable code for programming one or more computers to perform a method comprising the steps of:

• (a) distributing latches among a first set of bins, wherein said first set of bins corresponds to a first level of said integrated circuit design;
• (b) performing topology selection between said first set of bins and a root for a first clock tree;
• (c) discarding all of said first clock tree outside of said first level;
• and
• (d) constructing clock tree segments for bins in each level of said integrated circuit design outside of said first level, wherein a clock tree for said integrated circuit design includes a clock tree segment associated with each level in said integrated circuit design, including a segment of said first clock tree from said first set of bins.

An apparatus, comprising:

• one or more storage devices;
• and
• one or more processors in communication with said one or more storage devices, said one or more processors perform a method for constructing a clock tree in an integrated circuit design, said method comprising the steps of:
• (a) distributing latches among a first set of bins, wherein said first set of bins corresponds to a first level of said integrated circuit design;
• (b) performing topology selection between said first set of bins and a root for a first clock tree;
• (c) discarding at least a portion of said first clock tree outside of said first level;
• and
• (d) performing topology selection between a second set of bins and a root for a second clock tree, wherein:
• said second set of bins corresponds to a second level of said integrated circuit design,
• said step (d) is based at least in part on said first clock tree, and
• said clock tree includes a portion of said first clock tree from said first set of bins and a portion of said second clock tree from said second set of bins.

An apparatus, comprising:

• one or more storage devices;
• and
• one or more processors in communication with said one or more storage devices, said one or more processors perform a method comprising the steps of:
• (a) distributing latches among a first set of bins, wherein said first set of bins corresponds to a first level of said integrated circuit design;
• (b) performing topology selection between said first set of bins and a root for a first clock tree;
• (c) discarding all of said first clock tree outside of said first level;
• and
• (d) constructing clock tree segments for bins in each level of said integrated circuit design outside of said first level, wherein a clock tree for said integrated circuit design includes a clock tree segment associated with each level in said integrated circuit design, including a segment of said first clock tree from said first set of bins.