Method for reducing design effect of wearout mechanisms on signal skew in integrated circuit design

Abstract

A method for reducing the effect of signal skew degradation in the design of an integrated circuit is provided. First, a circuit design library is created describing library cells as a function of one or more environmental variable, wherein the one or more environmental variable includes a skew degradation variable indicating skew degradation of a signal as a function of a total number of signal switches of the signal. Then, the integrated circuit design is modeled utilizing the circuit design library to determine a first skew degradation for each of the first and second signals at a first predetermined number of signal switches, and a second skew degradation for each of the first and second signals for a second predetermined number of signal switches, and further to determine a first relative skew degradation for a first predetermined number of signal switches and a second relative skew degradation for a second predetermined number of signal switches, wherein a relative skew degradation is equal to the difference of the skew degradation of the first signal and the skew degradation of the second signal for a given number of signal switches. Next, a skew shift equal to the difference between the first relative skew degradation and the second relative skew degradation is calculated. Finally, the integrated circuit design is modified such that a skew degradation of the first signal at the first predetermined number of signal switches is determined to be equal to the first skew degradation of the first signal minus half of the skew shift.

Dependencies are inferred from the claim text.