Generation of refined switching windows in static timing analysis
AssigneeInternational Business Machines Corporation
InventorsRobert J. Allen, Ravishankar Arunachalam, David J. Hathaway
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Abstract
A method and structure to determine timing windows in a static timing analysis of an integrated circuit design, determines for at least one node in the integrated circuit design, an initial set of sub-windows and merges the sub-windows of the initial set into a final set of sub-windows.
Claims38
A method of determining timing windows in a static timing analysis of an integrated circuit design, said method comprising:
- determining, for at least one node in said integrated circuit design, an initial set of sub-windows;
- and
- merging said sub-windows of said initial set into a final set of at least two sub-windows.
A method of determining timing windows in a static timing analysis of an integrated circuit design, said method comprising:
- determining, for at least one node in said integrated circuit design, an initial set of sub-windows;
- and
- merging said sub-windows of said initial set into a final set of at least two sub-windows, wherein said timing windows are victim windows and the computation of said windows is performed in a direction opposite to that in which signals travel through said integrated circuit.
A method of determining timing windows in a static timing analysis of an integrated circuit design, said method comprising:
- determining, for at least one node in said integrated circuit design, an initial set of sub-windows;
- merging said sub-windows of said initial set into a final set of sub-windows by finding a set of largest intervals between said sub-windows of said initial set, the number of intervals in said set being less than or equal to one less than said maximum number of sub-windows;
- and
- combining sub-windows separated by intervals not in said set of largest intervals.
A method of determining whether an adjacent aggressor net may switch during a victim window of a victim net in a static timing analysis of an integrated circuit design, said method comprising:
- a) checking for overlap between said victim window and a switching window of said aggressor net;
- b) translating said victim net to a context of each input of said aggressor net, if said checking step identified an overlap;
- c) determining an initial set of aggressor sub-windows, if said checking step identified an overlap, and merging said aggressor sub-windows of said initial set into a final set of aggressor sub-windows,
- d) repeating said checking for each said aggressor sub-windows and translated victim window;
- and
- e) determining that said aggressor net may switch during said victim window only if said checking step found an overlap and at least one of said repeating steps determined that said input could switch during said translated victim window.
A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform a method of determining timing windows in a static timing analysis of an integrated circuit design, said method comprising:
- determining, for at least one node in said integrated circuit design, an initial set of sub-windows;
- and
- merging said sub-windows of said initial set into a final set of at least two sub-windows.
A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform a method of determining timing windows in a static timing analysis of an integrated circuit design, said method comprising:
- determining, for at least one node in said integrated circuit design, an initial set of sub-windows:
- and merging said sub-windows of said initial set into a final set of at least two sub-windows, wherein said timing windows are victim windows and the computation of said windows is performed in a direction opposite to that in which signals travel through said integrated circuit.
Dependencies are inferred from the claim text.