Method for generating transition delay fault test patterns

A method for generating transition fault test patterns for a circuit design, comprising:

• obtaining a first circuit model corresponding to the circuit design;
• replicating the first circuit model to obtain a second circuit model;
• selecting a storage device within the first circuit model:
• disconnecting a data input of the storage device in the first circuit model;
• disconnecting a data output of a corresponding storage device in the second circuit model;
• coupling a driver of the storage device in the fist circuit model to a portion of the second circuit model that was driven by the data output of the corresponding storage device in the second circuit model, wherein the first and second circuit models form a transformed circuit model;
• and
• using the transformed circuit model to generate transition fault test patterns for the circuit design, wherein using the comprising:
• performing automatic test pattern generation (APTG) on the transformed circuit model to obtain stuck-at-fault patterns for a set of stuck-at faults of the second circuit model;
• translating the stuck-at fault patterns to obtain transition fault test patterns for the circuit design;
• and
• performing fault simulation of the transition fault test patterns on the circuit design to determine a subset of stuck-at faults within the set of stuck-at faults that were not satisfied.

A method for generating transition fault test patterns for a circuit design, comprising:

• obtaining a first circuit model corresponding to the circuit design;
• replicating the first circuit model to obtain a second circuit model;
• selecting a storage device within a feedback path of the first circuit model;
• disconnecting a data input of the storage device in the first circuit
• disconnecting a data output of a corresponding storage device in the second circuit model;
• coupling a driver of the storage device in the fist circuit model to a portion of the second circuit model that was driven by the data output of the corresponding storage device in the second circuit model, wherein the first and second circuit models form a transformed circuit model;
• and
• using the transformed circuit model to generate transition fault test patterns for the circuit design.

A system for generating transition fault test patterns for a circuit design, comprising:

• receiving means for obtaining a first circuit model corresponding to the circuit design;
• replicating means coupled to the receiving means for replicating the first circuit model to obtain a second circuit model;
• selection means coupled to the replicating means for selecting a storage device within the first circuit model;
• transformation means coupled to the selection means, comprising:
• means for disconnecting a data input of the storage device in the first circuit model;
• means for disconnecting a data output of a corresponding storage device in the second circuit model;
• and
• means for coupling a driver of the storage device in the first circuit model to a portion of the second circuit model that was driven by the data output of the corresponding storage device in the second circuit model, wherein the first and second circuit models form a transformed circuit model;
• and
• test generating means coupled to the transformation means, for using the transformed circuit model to generate transition fault test patterns for the circuit design.

A system for generating transition fault test patterns for a circuit design, comprising:

• means for receiving a received circuit model corresponding to the circuit design;
• means for generating a first circuit model from the received circuit model and corresponding to the circuit design, the first circuit model being a replica of the received circuit model;
• replicating means coupled to the means for receiving, the replicating means replicating the first circuit model to obtain a second circuit model;
• selection means coupled to the replicating means for selecting a storage device within the first circuit model;
• transformation means coupled to the selection means, comprising:
• means for disconnecting a data input of the storage device in the first circuit model;
• means for disconnecting a data output of a corresponding storage device in the second circuit model;
• and
• means for coupling a driver of the storage device in the first circuit model to a portion of the second circuit model that was driven by the data output of the corresponding storage device in the second circuit model, wherein the first and second circuit models form a transformed circuit model;
• and
• test generating means coupled to the transformation means, for using the transformed circuit model to generate transition fault test Patterns for the circuit design, wherein the test generating means comprises:
• automatic test pattern generation means (ATPG) for performing automatic test pattern generation on the transformed circuit model to obtain stuck-at faults of the second circuit model;
• translating means coupled to the automatic test pattern generation means, for translating the stuck-at fault patterns to obtain transition fault test patterns for the circuit design;
• and
• fault simulation means coupled to the translating means, for performing fault simulation of the transition fault test patterns on the circuit design to determine a subset of stuck-at faults within the set of stuck-at faults that were not satisfied.

A method for generating transition fault test patterns for a circuit design, comprising:

• obtaining a first circuit model corresponding to the circuit design;
• replicating the first circuit model to obtain a second circuit model;
• selecting predetermined circuitry within the first circuit model;
• disconnecting a data input of the predetermined circuitry in the first circuit model;
• disconnecting a data output of corresponding circuitry in the second circuit model;
• coupling the data input of the predetermined circuitry in the first circuit model to a portion of the second circuit model that was driven by the data output of the corresponding circuitry in the second circuit model, wherein the first and second circuit models form a transformed circuit model;
• and
• providing the transformed circuit model, wherein the transformed circuit model is used for generating transition fault test patterns for the circuit design.