Logic circuit design method and cell library for use therewith

A logic circuit design method utilizing a computer system, said design method comprising the steps of:

• inputting a first logic circuit comprising a plurality of gates;
• generating a second logic circuit by replacing the gates of said first logic circuit by logically equivalent functional selector cells having two inputs and one output;
• generating a third logic circuit by modifying said second logic circuit to reduce the number of stages of at least a critical path within said second logic circuit;
• and
• outputting a fourth logic circuit generated by mapping said third logic circuit to a CMOS logic circuit through the use of a first library in which delay information and logical function information about a group of cells constituting a CMOS logic circuit have been stored and a second library containing the descriptions of the names, logical functions, and pin names of said functional selector cells having two inputs and one output, said first and second libraries are included in said computer system,
• wherein said fourth logic circuit does not include any of said functional selector cells having two inputs and one output.

A logic circuit design method utilizing a computer system, said design method comprising the steps of:

• inputting a first logic circuit comprising a plurality of gates;
• generating a second logic circuit by replacing the gates of said first logic circuit by logically equivalent functional selector cells having two inputs and one output;
• generating a third logic circuit by modifying said second logic circuit to reduce the number of stages of paths within said second logic circuit;
• and
• outputting a fourth logic circuit generated by mapping said third logic circuit to a CMOS logic circuit through the use of a library included in said computer system,
• wherein said fourth logic circuit does not include any of said functional selector cells having two inputs and one output.