Viterbi decoding apparatus and viterbi decoding method
AssigneeSony Corporation
InventorsToshiyuki Miyauchi, Masayuki Hattori
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AssigneeSony Corporation
InventorsToshiyuki Miyauchi, Masayuki Hattori
Estimating the term…
Three dual-port RAMs of the number of bits=8 and the number of words=4 are provided in a path memory circuit. Path selection information is sequentially written into the three RAMs every clock in accordance with the control of a control circuit. On the other hand, the path selection information is read out every clock from the RAMs in accordance with the control of the control circuit and is inputted as read path selection information or the like to a tracing circuit. The tracing circuit executes the tracing operation as many as three times on the basis of the read path selection information and trace starting state information which is formed by the control circuit. On the basis of a tracing result, the decoding data and a trace starting state in the subsequent clock are obtained.
A Viterbi decoding apparatus which has a path memory for storing selection information of a path for each transition state of a convolution code and which traces the information held in the path memory by an amount corresponding to a traceback depth, thereby performing a Viterbi decoding, wherein the path memory comprises:
A Viterbi decoding method of storing selection information of a path for each transition state of a convolution code and tracing the stored information by an amount corresponding to a traceback depth, thereby performing a Viterbi decoding, comprising a tracing step of performing tracing operations as many as a plurality of times for a period of time of one clock using a plurality of single-port rewritable memories provided in a path memory, such that performance of only one read operation or write operation happens on each of the plurality of single-port rewritable memories during a single clock,
Dependencies are inferred from the claim text.