Recording/reproduction device, semiconductor memory, and memory card using the semiconductor memory

A recording/reproduction device comprising:

• a controller section having an external interface which transacts data with outside, a first error correction code generator which generates a first error correction code for input data, and a first error corrector which implements an error detection and correction by using the first error correction code;
• and
• a semiconductor memory section having a second error correction code generator which generates a second error correction code, which is a BCH code in a same Galois field as the first error correction code and has a continuous root, for the first error correction code provided by said controller section, a memory which stores the data from said controller section, a first error correction code check symbol which is the first error correction code, with the data being excluded therefrom, and a second error correction code check symbol which is the second error correction code, with the data and first error correction code check symbol being excluded therefrom, and a second error corrector which implements an error detection and correction by using the data and first and second error correction code check symbols read out of said memory,
• wherein said controller section implements an error correction by using and error correction result provided by said semiconductor memory section.

A recording/reproduction device comprising:

• a controller section having an external interface which transacts data with outside, a first error correction code generator which generates a first error correction code for input data, and a first error corrector which implements an error detection and correction by using the first error correction code;
• and
• a semiconductor memory section having a second error correction code generator which generates a second error correction code, which is a BCH code in a same Galois field as the first error correction code and has a continuous root, for the first error correction code provided by said controller section, a memory which stores the data from said controller section, a first error code check system symbol which is the first error correction code, with the data being excluded therefrom, and a second error correction code check symbol which is the second error correction code, with the data and first error correction code check symbol being excluded therefrom, a second error correction which implements an error detection and correction by using the data and first and second error correction code check symbols read out of said memory, a correction information indicator which indicates information on whether or not said error correction has corrected the data and first error correction code check symbol, information of an intermediate error correcting computation and information of detected error positions and error values to said first error corrector, and a data sender which sends the data and first error correction code check symbol read out of said memory or data corrected by said error corrector and the first error correction code check symbol to said first error corrector,
• wherein said first error corrector detects an error by using the data and first error correction code check symbol provided by said data sender and, if said second error corrector has corrected the data, restores error-incorrected data by using the positions and error values and, if error is detected in the restored data and the first error correction code check symbol, implements an error correction for restored data by using the first error correction code check symbol and information of computation, and implements the error detection by using the first error correction code, or, if said error corrector has failed in data correction, attempts error correction for the error-incorrected data by using the first error correction code check symbol and information of computation and, if the error correction fails, attempts error correction for the restored data or the error-incorrected data by using the first error correction code check symbol.

A recording/reproduction device comprising:

• a controller section having an external interface which transacts data with outside, a first error correction code generator which generates a first error correction code for input data, and a first error corrector which implements an error detection and correction by using the first error correction code;
• and
• a semiconductor memory section having a second error correction code generator which generates a second error correction code, which is a BCH code in a same Galois field as the first error correction code and has a continuous root, for the first error correction code provided by said controller section, a memory which stores data from said controller section, a first error correction code check symbol which is the first error correction code, with the data being excluded therefrom, and a second error correction code check symbol which is the second error correction code, with the data and first error correction code check symbol being excluded therefrom, and a second error corrector which implements the error detection and correction by using the data and first and second error correction code check symbols read out of said memory,
• wherein said controller section, upon detecting an error, implements an error correction based on the first error correction code check symbol and information of computation provided by said semiconductor memory section and, upon falling in error correction, implements an error correction for the data read out of said memory by using the first error correction code check symbol.

A recoding/reproduction device comprising:

• a controller section having an external interface which transacts data with outside, a first error correction code generator which generates a first error correction code for input data, and a first which implements an error detection and correction by using the first correction code;
• and
• a semiconductor memory section having a second error correction code generator which generates a second error correction code, which is a BCH in a same Galois field as the first correction code and has a continuous root, for the first error correction code provided by said controller section, a memory which stores the data, a first error correction code check symbol which is the first error correction code, with the data being excluded therefrom, and a second error correction code check symbol which is the second error correction code, with the data and first error correction code check symbol being excluded therefrom, a second error corrector which implements the error detection and correction by using the data and first and second error correction code check symbols read out of said memory, an information indicator which indicates information on whether or not said second error corrector has detected an error, information on whether or not the data and first error correction code check symbol have been corrected and information of the intermediate error correcting computation to said first error corrector, and a data sender which sends the data and first error correction code check symbol read out of said memory and the data and first error correction code check symbol which are corrected by said second error corrector to said first error corrector,
• wherein said first error corrector, in case said second error corrector has not detected an error but detected an error in the data read out of said memory by using the first error correction code check symbol, or in case said second error corrector has failed in data correction but detected an error in the data read out of said memory by using the first error correction code check symbol, or in case said second error corrector has detected an error by using the first error correction code check symbol in the data which has been corrected by said second error corrector, attempts an error correction for the data read out of said memory by using the first error correction code check symbol and information of computation and, if error correction fails, attempts error correction for the data read out of said memory by using the first error correction code check symbol.

A memory card comprising:

• a card controller section having a first error correction code generator generates a first error correction code for data put in from outside, and a first error corrector which implements an error detection and correction by using the first error correction code;
• a semiconductor memory section having a second error correction code generator which generates a second error correction code for the data and first error correction code provided by said card controller section, a memory which stores the data from the card controller section, a first error correction code check symbol which is the first error correction code, with the data being excluded therefrom, and a second error correction code check symbol which is the second error correction code, with the data and first error correction code check symbol being excluded therefrom, and a second error corrector which implements an error detection and correction by using the data and first and second error correction code check symbols read out of said memory;
• and
• a connecting section which transacts data with an external device,
• wherein the second error correction is a BCH code in a same Galois field as the first error correction code and has a continuous root, and said card controller section implements an error correction by using and error correction result provided by said second error corrector.

A memory card comprising:

• a card controller section having an external interface which transacts data with outside, a first error corrector code generator which a first error correction code for input data, and a first error corrector which implements an error detection and correction by using the first error correction code;
• a semiconductor memory section having a second error correction code generator which generates a second error correction code, which is a BCH code in a same Galois field as the first error correction code and has a continuous root, for the data and first error correction code provided by said card controller section, a memory which stores the data from said card controller section, a first error correction code check symbol which is the first error correction code, with the data being excluded therefrom, and a second error correction code check symbol which is the second error correction code, with the data and first error correction code check symbol being excluded therefrom, and a second error corrector which implements error detection and correction by using the data and first and second error correction code check symbols read out of said memory;
• and
• a connecting section which transacts data with an external device,
• wherein said card controller section, upon detecting an error, implements an error correction based on the first error correction code check symbol and information of computation provided by said semiconductor memory section and, upon failing in error correction, implements and error correction for the data read out of said memory by using the first error correction code check symbol.