Modular architecture for memory testing on event based test system

An event based test system for testing semiconductor devices, comprising:

• two or more tester modules each having a plurality of pin units where each pin unit corresponds to a DUT pin of a semiconductor device under test (DUT), each of the tester modules operating independently from one another, and each pin unit being configured as an event tester;
• a main frame for accommodating the two or more tester modules therein;
• a test fixture provided on the main frame for electrically connecting the tester modules and the DUT;
• a host computer for controlling an overall operation of the test system by communicating with the tester modules;
• and
• means for producing event data off-line to generate a memory test pattern by specifying a test pattern algorithm and information regarding the design and configuration of a memory under test which is an embedded memory in the DUT or a stand-alone memory where the event data is created in a design stage of the memory under test through logic simulation;
• wherein the event data for generating the memory test pattern is provided to the host computer and is transferred to the tester module prior to testing the memory under test, and wherein the memory test pattern is generated based on the event data of the memory under test where a sequence of the event data is modified by an algorithmic test pattern selected for the memory under test, and wherein the means for producing the event data off-line are software routines written in a high level language including C/C++ languages.