US 6,651,199 B1Granted

In-system programmable flash memory device with trigger circuit for generating limited duration program instruction

AssigneeXilinx, Inc.

InventorFarshid Shokouhi

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Abstract

A trigger circuit for an In-System Programmable (ISP) memory device that operates with a JTAG interface. The trigger circuit receives instruction signals from the JTAG control circuitry, and limits the duration of these instruction signals to avoid erroneously repeating ISP programming operations. The trigger circuit includes a first logic circuit, a delay circuit, and a second logic circuit. The first logic circuit generates a logic high output when both the JTAG RUN-TEST and a program instruction signal are simultaneously asserted, and causes the second logic circuit to toggle the limited duration instruction signal into a logic high state. The delay circuit also detects the simultaneous assertion of the JTAG RUN-TEST and a program instruction signal, and generates a cancellation signal after a predetermined number of clock cycles. The cancellation signal causes the second logic circuit to toggle the limited duration instruction signal into a logic low state.

Claims20

Dependent claims

A trigger circuit for generating an instruction signal utilized by a control state machine in an In-System Programmable (ISP) memory device, the ISP memory device including a JTAG circuit having a standard TAP controller for generating a RUN-TEST signal when the TAP controller is in a RUN-TEST/IDLE state, and an instruction register circuit for generating a first instruction signal, the trigger circuit comprising:

a first logic circuit for generating a logic high output signal when both the RUN-TEST signal and the first instruction signal are in a first logic state;
a delay circuit for receiving the RUN-TEST signal and for generating a logic high output signal a predetermined number of clock cycles after the RUN-TEST signal changes to the first logic state;
an inverter connected to an output terminal of the delay circuit;
and
a second logic circuit having a first input terminal connected to an output terminal of the first logic circuit, a second input terminal connected to an output terminal of the inverter, and an output terminal connected to an input terminal of the control state machine,
wherein the trigger circuit transmits a second instruction signal to the control state machine in response to the RUN-TEST signal and the first instruction signal being in the first logic state, wherein the second instruction signal is maintained in the first logic state for the predetermined number of clock cycles, thereby avoiding erroneous operation of the control state machine caused when the RUN-TEST signal and the first instruction signal remain in the first logic state for an extended period.

3 more elements

a first means for initiating a first logic state of a second instruction signal when both the RUN-TEST signal and the first instruction signal are switched to a first logic state;
a second means for transmitting said second instruction signal to said control state machine;
and
a third means for maintaining said instruction signal in a first logic state for a predetermined number of clock cycles, wherein erroneous operation of the control state machine is thereby avoided when the RUN-TEST signal and the first instruction signal remain in the first logic state for an extended period.

1 more element

A method for generating an instruction signal utilized by a control state machine in an In-System Programmable (ISP) memory device, the ISP memory device including JTAG circuit having a standard TAP controller for generating a RUN-TEST signal when the TAP controller is in a RUN-TEST/IDLE state, and an instruction register circuit for generating a first instruction signal, comprising the steps of:

initiating a first logic state of a second instruction signal in response to both the RUN-TEST signal and the first instruction signal switching to a first logic state;
transmitting the second instruction signal to the control state machine;
and
maintaining said second instruction signal in a first logic state for a predetermined number of clock cycles,
wherein erroneous operation of the control state machine is thereby avoided when the RUN-TEST signal and the first instruction signal remain in the first logic state for an extended period.

2 more elements

Dependencies are inferred from the claim text.