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AssigneeSilicon Graphics, Inc.
InventorsPaul T. Wildes, Edward J. O'Neill
Estimating the term…
A method for determining optimum locations for scan latches using traditional fault-simulation and some additional ‘bookkeeping.’ A logic simulation is run on the IC, with single stuck-at faults injected into the circuit. The entire test set is run and records are kept of which faults are detected at every latch in the system. After the simulation run, the statistics gathered are used to indicate which system latches are the best candidates for conversion to scan latches: A high count of faults indicates high observability at that point. This can be further refined by looking at total faults covered by given sets of latches. This permits maximizing fault coverage while minimizing resources. In addition, the software can keep a transition count at each latch's output, to enable the already established method of using transition counts to measure testability. A low transition count indicates a desirable place for a scan latch.
A method for placing scan latches in a logic chip, said method comprising:
An apparatus for simulating designed logic comprising:
A method for placing scan latches in a logic chip, said method comprising:
A logic chip comprising:
Dependencies are inferred from the claim text.