Semiconductor device having test mode entry circuit

A semiconductor device having a test mode, the device comprising:

• a decision circuit for determining whether the test mode has been entered to output test mode entry signal;
• and
• a timer circuit, connected to the decision circuit, for performing a timing operation in response to the test mode entry signal and producing a time-up signal after a predetermined time has elapsed, wherein the decision circuit invalidates the test mode entry signal in response to the time-up signal.

A semiconductor device having a test mode, the device comprising:

• a decision circuit for determining whether the test mode has been entered based on a sequential receipt of a plurality set of test mode command signals to output a decision signal;
• and a mode register coupled to the decision circuit for setting a test mode in response to the decision signal.

A semiconductor device comprising:

• a first operation mode entry circuit for producing a first operation mode signal in response to an external signal after a power-on, the first operation mode entry circuit including an operation mode decision circuit for invalidating the first operation mode signal in response to the external signal until a power-off once the first operating mode signal has been produced.

A semiconductor device comprising:

• a first operation mode entry circuit for producing a first operation mode signal in response to a first combination on a logic value of a plurality of external signals after a power-on, the first operation mode entry circuit including an operation mode decision circuit for invalidating the first operation mode signal in response to a transition from the first combination to a second combination of the external signal until a power-off once the first operating mode signal has been Produced.

A semiconductor device with a function which masks a plurality of I/O data groups including a first I/O data group and a second I/O data group in accordance with a plurality of mask signals including first and second mask signals, the device comprising:

• a plurality of data I/O terminal groups including a first data I/O terminal group and a second data I/O terminal group, wherein the semiconductor device masks the second I/O data group corresponding to the second data I/O terminal group in accordance with the second mask signal;
• and
• a first data compression circuit for compressing a first output data group and supplying the compressed first output data group to one terminal of the first data I/O terminal group.