Method for allowing distributed high performance coherent memory with full error containment
AssigneeHewlett-Packard Development Company, L.P.
InventorsKent A. Dickey, Michael L. Ziegler
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Abstract
The present invention provides for a method and system for ensuring error containment in packet based systems which are capable of large scaleability. In operation, an error bit travels with each data packet and if the bit is set, any device which receives the data packet acts to contain that packet. Thus, the error message travels only as far as the error data and does not stop processing at locations not affected by the error. Any system resource, upon receipt of a set error bit, must act to correct the fault.
Claims6
A distributed high performance coherent memory module with error containment, comprising:
- a reading module for reading an error indication included in a packet reflective of a current state of a unit;
- a determination module for determining if said state of a unit is in error mode;
- a permission module for permitting a set of network traffic to operate in a normal state if said state of said unit is not in error mode;
- a driving module for driving an error indicator to a subject processor if said state of said unit is in error mode;
- a blocking module for ensuring that a set of corrupt traffic does not reach I/O devices if said current state of unit is in error mode;
- a second reading module for ensuring that each member of a group of connected units reads said error indication included in said packet, if said state of said unit is in error mode;
- a shared memory bit module therein for providing a shared memory bit within said error indication and further comprising a shared memory area within said unit;
- and
- means for moving said error indication coextensive only with errors in particular data.
Dependencies are inferred from the claim text.