Clocking scheme for programmable logic device
AssigneeCypress Semiconductor Corporation
InventorTimothy M. Lacey
Life of this patent
Estimating the term…
Abstract
A programmable logic device comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a first plurality of clock signals in response to (i) one or more input clock signals and (ii) a configuration signal. The second circuit may be configured to generate a second plurality of clock signals in response to (i) said first plurality of clock signals and (ii) said configuration signal. The third circuit may be configured to present a third plurality of clock signals selected from (i) said one or more input clock signals, (ii) said second plurality of clock signals in response to said configuration signal.
Claims17
A programmable logic device comprising:
- a phase lock loop configured to generate (a) a first plurality of clock signals, (b) a status signal and (c) an output signal in response to (i) one or more input clock signals, (ii) a configuration signal and (iii) a feedback signal;
- a second circuit configured to generate a second plurality of clock signals in response to (i) said first plurality of clock signals and (ii) said configuration signal;
- and
- a third circuit configured to present a third plurality of clock signals selected from (i) said one or more input clock signals and (ii) said second plurality of clock signals in response to said configuration signal.
A programmable logic device comprising:
- means for generating (a) a first plurality of clock signals, (b) a status signal and (c) an output signal in response to (i) one or more input clock signals, (ii) a configuration signal and (iii) a feedback signal;
- means for generating a second plurality of clock signals in response to (i) said first plurality of clock signals and (ii) said configuration signal;
- and
- means for presenting a third plurality of clock signals selected from (i) said one or more input clock signals and (ii) said second plurality of clock signals in response to said configuration signal.
A method for providing global clock signals in a programmable logic device comprising the steps of:
- (A) generating (a) a first plurality of clock signals, (b) a status signal and (c) an output signal in response to (i) one or more input clock signals, (ii) a configuration signal and (iii) a feedback signal;
- (B) generating a second plurality of clock signals in response to (i) said first plurality of clock signals and (ii) said configuration signal;
- and
- (C) presenting a third plurality of clock signals selected from (i) said one or more input clock signals and (ii) said second plurality of clock signals in response to said configuration signal.
Dependencies are inferred from the claim text.