Method and apparatus for generating timeouts to a system based counting intervals supplied by a shared counting device
AssigneeHewlett-Packard Development Company, L.P.
InventorJohn A. Wickeraad
Life of this patent
Estimating the term…
Abstract
A timeout mechanism that can accommodate an improved accuracy in determining the timeout of a pending transaction while conserving the amount of processing circuitry is herein disclosed. A fetch state machine is associated with each cache line. When the cache line is fetched from memory, the fetch state machine tracks the number of timeout periods that lapse before the cache line is retrieved. If a predetermined number of timeout periods lapses before the cache line is retrieved, a timeout occurs and processed accordingly.
Claims17
A computer system, comprising:
- a memory storage device having a plurality of transactions, each transaction receiving a response;
- a counter device that generates a pulse at a specified time interval;
- and
- a plurality of timeout devices, each timeout device coupled to the counter device, each timeout device corresponding to a select one of the transactions, each timeout device having:
- an initiator mechanism that starts the timeout device when the corresponding transaction is initiated;
- a tracking mechanism that maintains a count of a number of pulses received from the counter device;
- a timeout mechanism that signifies a time out when the number of pulses meets a threshold and the threshold is satisfied before the response is received;
- and
- a reset mechanism that resets the tracking mechanism when the response is received before the threshold is satisfied.
A time-out control unit comprising:
- an event-initiation input;
- an event-outcome input;
- a number of state machines, each state machine having a set input and a clear input, each state machine, following reception of a set signal from the set input, outputting a timeout signal after internally transitioning a number of internal states prior to reception of a clear signal from the clear input;
- a first decoder that receives an event-initiation signal from the event-initiation input and, in response, sets a state machine;
- and
- a second decoder that receives an event-outcome signal from the event-outcome input and, in response, clears a state machine.
A method for timing an operation, the method comprising:
- providing a time-out control unit having
- an event-initiation input,
- an event-outcome input, and
- a number of state machines, each state machine having a set input and a clear input, each state machine, following reception of a set signal from the set input, outputting a timeout signal after internally transitioning a number of internal states prior to reception of a clear signal from the clear input, a particular state machine set upon reception of an event-initiation signal by the time-out control unit;
- upon launching the operation, inputting to the event-initiation input of the time-out control unit an event initiation signal;
- when the operation completes, inputting to the event-outcome input of the time-out control unit an event outcome signal;
- and
- when a timeout signal is generated by a state machine, detecting the timeout signal as an operation-timed-out event.
Dependencies are inferred from the claim text.