Delay time judging apparatus

A delay time judging method of judging whether or not delay time of a delay circuit for delaying an input signal is equal to a desired delay time, the method comprising:

• generating a shift clock having a phase that is delayed by a predetermined amount relative to a phase of the input clock signal;
• comparing a phase of a delay clock which is obtained by delaying the input clock signal by the delay circuit, to that of the shift clock;
• judging whether or not the phase of the shift clock matches that of the delay clock;
• and
• repeating said generating the shift clock, said comparing the phase and said judging until the phase of the delay clock matches that of the shift clock.

Semiconductor device testing apparatus for testing a semiconductor device, comprising:

• a variable delay circuit having a plurality of delay paths;
• a shift clock supply unit which supplies a shift clock having a desired delayed time and phase relative to a reference clock;
• a phase comparing unit which compares a phase of the shift clock to a phase of a delay clock for which the reference clock is delayed by the delay circuit, so as to output a comparison signal;
• a judging unit which judges whether or not the delay time of the variable delay circuit is equal to the desired delay time;
• a timing generator including a linearization memory which stores a delay path necessary to generate the desired delay time based on the comparison signal;
• a pattern generator which generates a test pattern to be input to the semiconductor device;
• a waveform shaper which outputs a waveform-shaped test pattern which shaped the test pattern so as to be suitable for the semiconductor device under test, based on the delay clock in which the reference clock is delayed by the delay paths stored in the linearization memory, and the test pattern;
• a contact portion which places the semiconductor device under test thereon and inputs the waveform-shaped test pattern to the semiconductor device under test;
• and
• a comparator which compares an output signal output from the semiconductor device which has input the waveform-shaped test pattern, to an expectation value which is expected to output from the semiconductor device under test and that is output from said generator.