Exception handling with reduced overhead in a multithreaded multiprocessing system

A method of performing exception handling in a multiprocessor computer comprising:

• executing a first thread on a first processor and a second thread on a second processor;
• detecting an exception in said first processor;
• saving a first state of said first processor as a regular state and a second state of said second processor as an extended state;
• storing control information which indicates that said first processor detected said exception;
• mapping an identification of said first processor to a first index and mapping an identification of said second processor to a second index;
• handling said exception;
• loading said regular state to a processor which is mapped to said first index and loading said extended state to a processor which is mapped to said second index, wherein said second processor is mapped to said first index and said first processor is mapped to said second index;
• mapping said first index to a processor which the control information indicates detected the exception and mapping the second index to a processor which did not generate the exception;
• and
• executing said first thread on said second processor and said second thread on said first processor.

A multiprocessor computer comprising:

• a slave processor configured to:
• detect an exception;
• and
• save control information, wherein said control information includes an indication of which processor detected said exception;
• a master processor configured to:
• receive notification of said detected exception from said slave processor;
• and
• save a first state of said master processor as an extended state in response to said notification;
• receive a copy of a second state of said slave processor;
• save said second state as a regular state of said master processor;
• and
• handle said exception;
• circuitry configured to:
• restore said regular state to said master processor;
• restore said extended state to said slave processor;
• and
• transfer said regular state from said master processor to said slave processor and loading said first extended state to said master processor, in response to detecting said control information indicates said slave processor detected said exception.

A multiprocessor computer comprising:

• a first processor configured to:
• execute a first thread;
• detect an exception;
• save a first state of said first processor as a regular state in response to said exception;
• store control information which indicates that said first processor detected said exception;
• handle said exception;
• a second processor configured to:
• execute a second thread;
• receive notification from said first processor of said detected exception;
• and
• save a second state of said second processor as an extended state;
• circuitry configured to:
• map an identification of said first processor to a first index and map an identification of said second processor to a second index;
• load said stored regular state to a processor which is mapped to said first index and load said stored extended state to a processor which is mapped to said second index, wherein said second processor is mapped to said first index and said first processor is mapped to said second index, and wherein said first thread is executed on said second processor and said second thread is executed on said first processor;
• and
• map said first index to a processor which the stored control information indicates detected the exception and map the second index to a processor which did not generate the exception.