Recursively accessing a branch target address cache using a target address previously accessed from the branch target address cache

A method for prefetching instructions following an instruction cache miss by a current address comprising:

• comparing selected bits from the current address with a set of indices to a branch target address cache;
• and
• in response to said step of comparing, when the selected bits match an index of the set of indices, performing accessing an address corresponding to the index from the branch target address cache;
• prefetching a stored address using the address accessed from the branch target address cache into a prefetch buffer;
• determining if an instruction corresponding to the current address has been accessed from memory;
• and
• if the instruction corresponding to the current address has not been accessed from memory, again comparing selected bits from the address accessed from the branch target address cache with the set of indices to the branch target address cache.

Instruction prefetching circuitry comprising:

• a branch target address cache for storing a plurality of addresses to stored instructions, each address associated with an index of a set of indices;
• control circuitry for comparing selected bits from a selected address with said set of indices and accessing a said address from said branch target address cache when said selected bits match a corresponding said index;
• circuitry for prefetching a stored instruction associated with said address accessed from said branch target address cache during an access of an instruction, at a current address, from a memory system at higher level than on-chip cache;
• wherein the circuitry for prefetching said stored instruction includes circuitry for
• determining if an instruction corresponding to a current address has been accessed from a memory;
• and
• if the instruction corresponding to the current address has not been accessed from said memory, again comparing selected bits from the address accessed from the branch target address cache with the set of indices to the branch target address cache.

A data processing system comprising:

• memory for storing instructions;
• a microprocessor coupled to said memory comprising:
• a branch target address cache for storing a plurality of addresses to stored instructions, said addresses associated with a set of indices;
• an instruction cache;
• and
• instruction prefetch circuitry operable to:
• compare selected bits from a current instruction address causing a miss to said instruction cache with said set of indices and when the selected bits match an index of the set of indices:
• access an address corresponding to the index from the branch target address cache;
• prefetch a stored address from a selected one of said instruction cache and said memory using the address accessed from the branch target address cache into a prefetch buffer;
• determine if an instruction corresponding to a current address has been accessed from said memory;
• and
• if the instruction corresponding to the current address has not been accessed from said memory, again compare selected bits from the address accessed from the branch target address cache with the set of indices to the branch target address cache.