Back to results
US 6,651,160 B1Granted
Register set extension for compressed instruction set
AssigneeMIPS Technologies, Inc.
InventorW. Patrick Hays
Life of this patent
Estimating the term…
Abstract
Systems and methods for extending register addresses in compressed instruction sets are capable of executing extended register instructions that supplement the bits needed to address registers. The extended register instruction precedes corresponding standard instruction, and register the bits from the extend instruction are combined with register bits from the standard instruction to obtain a longer register address.
Claims22
A method for extending registers comprising:
- reading a first instruction;
- determining whether the first instruction is an extend register instruction;
- reading a second instruction;
- and
- combining register bits in the first instruction with register bits in the second instruction to form an extended register address when the first instruction is an extend register instruction.
2 more elements
A digital signal processor comprising:
- a set of addressable registers;
- instruction storage providing a first and second instruction;
- and
- an instruction decoder capable of:
- determining whether the first instruction is an extend register instruction, and combining bits from the first instruction with bits in the second instruction to form an extended register address.
2 more elements
Dependencies are inferred from the claim text.