Floating point register stack management for CISC
AssigneeATI International SRL
InventorsTiruvur R. Ramesh, Sanjay Mansingh, Korbin Van Dyke
Life of this patent
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Abstract
A floating point register stack for a processor combines a plurality of two general purpose registers to form a register stack for x86 instructions and leaves the remaining general purpose registers for native instructions of the processor. By mapping x86 sources into the stack of two general purpose registers and operating x86 instructions on the x86 stack, the register stack for the processor is able to support both the processor's native instruction set and the x86 instruction set without increasing the size of the register stack.
Claims12
A shared register system for a multi-instruction-set floating point processor, the shared register system comprising:
- a set of first data registers, wherein the width of each of said first data registers supports a first instruction set;
- a set of second data registers, wherein each of said second data registers comprises a plurality of said first data registers, and wherein the width of each of said second data registers supports a second instruction set;
- and
- an N-bit pseudo-tag register, wherein each bit in said pseudo-tag register represents the state of a corresponding one of said second data registers.
Dependencies are inferred from the claim text.