Determination of approaching instruction starvation of threads based on a plurality of conditions
AssigneeIntel Corporation
InventorsDavid W. Burns, James D. Allen, Michael D. Upton, Darrell D. Boggs, Alan B. Kyker
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Abstract
In a multi-threaded processor, thread priority variables are set up in memory. According to an embodiment of the present invention, several conditions are monitored so as to determine an indication of instruction side starvation may be approaching. If such starvation is approaching, the starvation is resolved upon the expiration of a threshold counter or the like.
Claims30
In a multi-threaded processor, a method of assigning thread priority comprising:
- determining whether a plurality of conditions are present in said processor;
- determining, based on satisfaction of said plurality of conditions, whether there is an indication of approaching instruction side starvation for a first thread of at least two threads.
In a processor to handle processing of at least first and second threads in parallel, a method of assigning thread priority comprising:
- determining if a plurality of conditions for said first thread are true, the conditions including
- if the processor is operating in a multithreaded processing mode;
- if the first thread has no instructions in an execution pipeline of said processor;
- and
- if the first thread is attempting to fetch instructions from a memory
- determining that there is an indication of approaching instruction side starvation for said first thread when said plurality of conditions are true.
A multi-threaded processor comprising:
- first and second thread queues;
- control logic coupled to said first and second thread queues, said control logic to determine whether a plurality of conditions are present in said processor, and determine that there is an indication of approaching instruction side starvation for a first thread of at least first and second threads based on satisfaction of said plurality of conditions.
A processor to handle processing of at least first and second threads in parallel comprising:
- first and second thread queues;
- control logic coupled to said first and second thread queues, said control logic to determine if a plurality of conditions are true and to determine whether instruction side starvation is approaching for said first thread based on said conditions, the conditions including
- if the processor is operating in a multithreaded processing mode;
- if the first thread has no instructions in an execution pipeline of said processor;
- and
- if the first thread is attempting to fetch instructions from a memory.
A computer system to handle processing of at least first and second threads in parallel comprising:
- a memory to store instructions for first and second threads;
- a processor coupled to said memory and including
- first and second thread queues to store instructions from said first and second threads;
- control logic coupled to said first and second thread queues, said control logic to determine whether a plurality of conditions in said processor are true, and determine whether there is an indication of approaching instruction side starvation for said first thread based on satisfaction of said plurality of conditions.
A computer system to handle processing of at least first and second threads in parallel comprising:
- a memory to store instructions for first and second threads;
- a processor coupled to said memory and including
- first and second thread queues to store instructions from said first and second threads;
- control logic coupled to said first and second thread queues, said control logic to determine if a plurality of conditions are true and to determine whether instruction side starvation is approaching for said first thread based on said conditions, the conditions including
- if the processor is operating in a multithreaded processing mode;
- if the first thread has no instructions in an execution pipeline of said processor;
- and
- if the first thread is attempting to fetch instructions from a memory.
A set of instructions residing in a storage medium, said set of instructions capable of being executed by a processor to handle processing of at least first and second threads in parallel and assign thread priority comprising:
- determining whether a plurality of conditions are present in said processor;
- determining whether there is an indication of approaching instruction side starvation for said first thread, based on satisfaction of said plurality of conditions.
Dependencies are inferred from the claim text.