Apparatus and method for translating a programmable logic device programmer object file
AssigneeAltera Corporation
InventorsVincent T. Bocchino, Colin Hendry, Stephane Cauneau, Virendra Patel
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Abstract
A circuit for translating a configuration file used to configure a programmable logic device includes a first register to serially receive configuration data. A second register receives, in parallel, configuration data from the first register. A translation address memory translates an original address for a selected configuration bit of the configuration data to a translated address. A translation memory stores the selected configuration bit at the translated address. Control logic selectively downloads configuration data from the translation memory to a programmable logic device core.
Claims19
A method of translating a configuration file for configuring a programmable logic device (PLD), said method comprising:
- shifting configuration data into a first register;
- loading, in parallel, said configuration data from said first register into a second register;
- shifting additional configuration data into said first register while performing the steps of:
- obtaining from a translation address memory a new address for a selected configuration bit in said second register,
- writing said selected configuration bit to said new address in a memory,
- repeating said obtaining and writing steps until all configuration bits in said second register have been processed;
- and
- downloading the contents of said memory to a programmable logic device core so as to configure said programmable logic device.
A circuit for translating a configuration file used to configure a programmable logic device (PLD), comprising:
- a first register to serially receive configuration data;
- a second register to receive, in parallel, configuration data from said first register;
- a translation address memory providing a translated address for a selected configuration bit;
- a translation memory to store said selected configuration bit in response to said translated address memory;
- and
- control logic to download configuration data from said translation memory to a programmable logic device core associable with the PLD.
A circuit for translating a first configuration file associable with a first programmable logic device (PLD) into a second configuration file associable with a second PLD.
A processing system comprising:
- a programmable logic device (PLD);
- and
- a circuit for translating a first configuration file used to configure the PLD;
- a register to receive configuration data of the first configuration file;
- a translation address memory to translate an original address for a selected configuration bit of said configuration data to a translated address associable with the PLD;
- a translation memory to store said selected configuration bit at said translated address;
- and
- control logic to selectively download configuration data from said translation memory to a programmable logic device core associable with the PLD.
Dependencies are inferred from the claim text.