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US 6,651,152 B1Granted
Microcomputer including download circuit controlling data download to plurality of memories
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsHiroshi Ueki, Teruaki Kanzaki
Life of this patent
Estimating the term…
Abstract
A microcomputer system having a central processor, a plurality of memory types and a bus interface circuit is configured to allow an external device to download and upload data to/from the various memories using a download circuit connected to the plurality of memories via the bus interface circuit. In operation, a first reset signal, a second reset signal and a mode set signal operate to control whether the central processor or the download circuit will be active, and whether a selector will couple the central processing unit or the download circuit to the bus interface circuit.
Claims20
A microcomputer comprising:
- a plurality of memories;
- a bus interface circuit connected to said plurality of memories through a bus group;
- a central processing unit to be coupled to said memories via said bus interface circuit, and operating using said memories, said central processing unit being reset in response to a reset signal to stop its operation;
- a download circuit coupled to said memories via said bus interface circuit, and carrying out data input/output with respect to said memories;
- a first reset signal generation circuit generating and applying to said central processing unit a first reset signal to reset said central processing unit;
- a second reset signal generation circuit generating and applying to said plurality of memories and said bus interface circuit a second reset signal according to a mode set signal specifying input/output execution with one of said memories using said download circuit and said first reset signal;
- and
- a selector selectively coupling said central processing unit and said download circuit to said bus interface circuit in response to said mode set signal.
5 more elements
A microcomputer comprising:
- a plurality of memories;
- a bus interface circuit connected to said plurality of memories through a bus group;
- a central processing unit to be coupled to said plurality of memories via said bus interface circuit, said central processing unit operating using said memories;
- a download circuit to be connected to said plurality of memories via said bus interface circuit, and carrying out data input/output with respect to said plurality of memories;
- a first reset signal generation circuit generating and applying to said central processing unit a first reset signal to reset said central processing unit;
- a second reset signal generation circuit generating and applying to said plurality of memories and said bus interface circuit a second reset signal according to a mode set signal and said first reset signal;
- a selector selectively coupling said central processing unit and said download circuit to said bus interface circuit in response to a predetermined selector control signal;
- and
- a selector control signal generation circuit generating and applying to said selector said selector control signal according to said mode set signal, an access request signal output to said bus interface circuit from said central processing unit and an access request signal output from said download circuit output to said bus interface circuit, and preferentially in response to the access request signal from said central processing unit.
6 more elements
A microcomputer comprising:
- a plurality of memories;
- a bus interface circuit connected to said plurality of memories through a bus group;
- a central processing unit connected to said plurality of memories via said bus interface circuit, and operating using said memory;
- a download circuit to be connected to said plurality of memories via said bus interface circuit, and carrying out data input/output with respect to said plurality of memories;
- and
- selective couple means connected to said central processing unit for selectively coupling one of said central processing unit and said download circuit to one of said memories corresponding to access request according to a logic value of a predetermined mode set signal, a logic value of an access request signal from said central processing unit to one of said plurality of memories, and a logic value of an access request from said download circuit to one of said plurality of memories.
3 more elements
Dependencies are inferred from the claim text.