MFENCE and LFENCE micro-architectural implementation method and system
AssigneeIntel Corporation
InventorsSalvador Palanca, Stephen A. Fischer, Subramaniam Maiyuran, Shekoufeh Qawami
Life of this patent
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Abstract
A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
Claims18
A system comprising:
- a memory unit;
- a processor comprising a memory ordering unit to receive a first instruction to prevent newer loads from retrieving data from said memory unit until older loads have been retired, said first instruction being dispatched from said memory ordering unit to a cache controller after said older loads have been retired;
- a bus to couple said memory unit to said processor.
A system comprising:
- a processor to fetch a first instruction to prevent a first memory access operation to be fetched after said first instruction from accessing memory until a second memory access operation to be fetched prior to said first instruction is retired;
- a memory unit coupled to said processor comprising data accessible by weakly-ordered memory access operations.
Dependencies are inferred from the claim text.