US 6,651,148 B2 · High-speed memory controller for pipelining memory read transactions

Abstract

A memory controller (218) is disclosed which includes a write arbiter (130) and a read arbiter (140) for receiving and processing memory requests from a number of requestor modules (190) for accessing a high speed memory device (110). A high speed controller (120) controls data flow to and from the high speed memory device (110) at a frequency that is higher than ail operating of the arbiters (130, 140), allowing pseudo-simultaneous memory transactions. A read data dispatcher (160) is also disclosed for receiving data from the high speed controller (120) in response to read transactions and for passing the data to one of the requestor modules (190). The size and destination information for launched read transactions are kept by a queue 150. When return data is received by the read data dispatcher (160), the read data dispatcher (160) matches the appropriate amount of data with each queue entry and delivers that return data to the appropriate requester module (190).

Claims7

Dependent claims

A memory controller for controlling memory transactions to and from a memory device in response to memory requests from requestor modules, said memory controller comprising:

at least one arbiter for receiving and processing said memory requests, each memory request being received from a corresponding requestor module;
a controller module for issuing at least memory read transactions to said memory device in response to signals from said at least one arbiter;
an address memory means for receiving the addresses of said requestor modules initiating said memory read transactions in the order that said controller module issued said memory read transactions to said memory device, and for issuing said addresses in said order;
and
a data dispatcher for receiving data from said controller module in response to said memory read transactions, for receiving a next address in said order from said address memory means, and for passing data associated with each memory read transaction to said corresponding requestor module, wherein said next address is used by said data dispatcher to identify said corresponding requestor module.

2 more elements

Dependencies are inferred from the claim text.

High-speed memory controller for pipelining memory read transactions

Life of this patent

High-speed memory controller for pipelining memory read transactions

Life of this patent

Abstract

Claims7