Back to results
US 6,651,129 B1Granted
Apparatus and method for establishing a data communication interface to control and configure an electronic system with analog and digital circuits
AssigneeNational Semiconductor Corporation
InventorsGregory J. Smith, Jeffrey P. Kotowski, William J. McIntyre
Life of this patent
Estimating the term…
Abstract
A system and method for providing for on-chip configuration, control and testing of mixed signal circuitry within an integrated circuit. A dual signal interface conveys the serial data and clock signals used for controlling the enablement, disablement and operational modes of the synchronous circuitry responsible for such on-chip configuration, control and testing, thereby minimizing the amount of overhead, in terms of interface terminals needed, for providing such capability.
Claims22
An apparatus including an integrated circuit with mixed signal circuitry and configuration, control and testing circuitry for said mixed signal circuitry, comprising:
- a plurality of input terminals for conveying a plurality of input signals including a plurality of configuration control signals;
- a plurality of interface terminals for conveying a plurality of interface signals including a plurality of analog interface signals;
- interface circuitry, coupled to said plurality of input terminals, that provides a plurality of configuration data and a plurality of switch control signals in response to said plurality of configuration control signals;
- memory circuitry, coupled to said interface circuitry, that stores said plurality of configuration data;
- analog circuitry with a plurality of internal circuit terminals and a plurality of external circuit terminals, coupled to said memory circuitry, that is electrically configurable and communicates a plurality of internal analog signals and a plurality of external analog signals via said plurality of internal circuit terminals and said plurality of external circuit terminals, respectively, in response to a portion of said plurality of configuration data;
- and
- switching circuitry, coupled between said plurality of internal circuit terminals, said plurality of external circuit terminals and said plurality of interface terminals, that alternately couples respective ones of said pluralities of internal and external circuit terminals to corresponding ones of said plurality of interface terminals in response to said plurality of switch control signals;
- wherein respective ones of said pluralities of internal and external analog signals change in response to corresponding changes in respective ones of said portion of said plurality of configuration data.
5 more elements
An apparatus including control circuitry with a dual signal interface for controlling enablement and disablement of a synchronous system, comprising:
- a data signal terminal for conveying a serial data signal with first and second opposing signal states and first and second opposing signal transitions between said first and second opposing data signal states;
- a clock signal terminal for conveying a clock signal with first and second opposing signal states and first and second opposing signal transitions between said first and second opposing clock signal states;
- and
- an enablement control circuit, coupled to said data and clock signal terminals, that provides
- an asserted system enablement control signal in response to said data and clock signals following reception of a predetermined sequence of said first and second opposing data signal states and said first and second opposing clock signal state transitions, wherein said predetermined sequence includes
- an initial first clock signal state transition coincident with said first data signal state and
- coincidence of respective ones of said first and second opposing data signal states and said first and second opposing clock signal state transitions, and
- a nonasserted system enablement control signal in response to said first clock signal state having a duration greater than a predetermined interval.
5 more elements
An apparatus including control circuitry with a dual signal interface for controlling a plurality of operational modes of a synchronous system, comprising:
- a data signal terminal for conveying a serial data signal with first and second opposing signal states and first and second opposing signal transitions between said first and second opposing data signal states;
- a clock signal terminal for conveying a clock signal with first and second opposing signal states and first and second opposing signal transitions between said first and second opposing clock signal states;
- and
- a mode control circuit, coupled to said data and clock signal terminals, that provides
- an asserted one of a plurality of operation mode control signals in response to said data and clock signals following reception of a predetermined sequence of said first and second opposing data signal states and said first and second opposing clock signal state transitions, wherein said predetermined sequence includes
- coincidence of said first clock signal state transitions with said second data signal state and
- coincidence of respective ones of said first and second opposing data signal states and said second opposing clock signal state transitions, and
- a plurality of nonasserted operation mode control signals in response to said first clock signal state having a duration longer than a predetermined interval.
5 more elements
An apparatus including control circuitry with a dual signal interface for controlling enablement, disablement and a plurality of operational modes of a synchronous system, comprising:
- a data signal terminal for conveying a data signal with first and second opposing signal states and first and second opposing signal transitions between said first and second opposing data signal states;
- a clock signal terminal for conveying a clock signal with first and second opposing signal states and first and second opposing signal transitions between said first and second opposing clock signal states;
- an enablement control circuit, coupled to said data and clock signal terminals, that provides
- an asserted system enablement control signal in response to said data and clock signals following reception of a predetermined sequence of said first and second opposing data signal states and said first and second opposing clock signal state transitions, wherein said predetermined sequence includes
- an initial first clock signal state transition coincident with said first data signal state and
- coincidence of respective ones of said first and second opposing data signal states and said first and second opposing clock signal state transitions, and
- a nonasserted system enablement control signal in response to said first clock signal state having a duration greater than a predetermined interval;
- and
- a mode control circuit, coupled to said enablement control circuit and said data and clock signal terminals, that provides
- an asserted one of a plurality of operation mode control signals in response to said asserted system enablement control signal and said data and clock signals following reception of a predetermined sequence of said first and second opposing data signal states and said first and second opposing clock signal state transitions, wherein said predetermined sequence includes
- coincidence of said first clock signal state transitions with said second data signal state and
- coincidence of respective ones of said first and second opposing data signal states and said second opposing clock signal state transitions,
- a plurality of nonasserted operation mode control signals in response to said first clock signal state having a duration longer than a predetermined interval, and
- said plurality of nonasserted operation mode control signals in response to said nonasserted system enablement control signal.
11 more elements
Dependencies are inferred from the claim text.