DMA controller which optimizes transfer rate of data and method therefor
AssigneeCanon Kabushiki Kaisha
InventorToshiaki Minami
Life of this patent
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Abstract
A DMA controller is arranged to transfer data in units of one byte, one by one, by hand shaking when a transfer request signal is asserted by a low-speed I/O device, and is arranged to continuously transfer data of a predetermined number of transfer units when a burst request signal is asserted by a high-speed I/O device. The burst request signal may be replaced with a number-of-transfer-bytes information signal to continuously transfer data of a number of transfer bytes designated by the number-of-transfer-bytes information signal. Accordingly, a rate of data transfer between an I/O bus and a system bus can be optimized according to the kind of an I/O device connected to the I/O bus.
Claims20
A DMA controller arranged to transfer data between a main storage connected to a system bus and an I/O device connected to an I/O bus, said DMA controller comprising:
- an FIFO memory arranged to buffer a difference in transfer speed between said system bus and said I/O bus;
- first transfer means for transferring data between said main storage and said FIFO memory through said system bus;
- request receiving means for receiving from said I/O device a request for transfer by DMA;
- second transfer means for transferring data of by every one transfer unit between said FIFO memory and said I/O device through said I/O bus when a request for normal transfer by DMA is received by said request receiving means;
- and
- third transfer means for continuously transferring data by a predetermined number of transfer units between said FIFO memory and said I/O device through said I/O bus when a request for continuous transfer by DMA is received by said request receiving means,
- wherein if a remainder of data to be transferred becomes less than the predetermined number of transfer units during a transfer by the predetermined number of transfer units by said third transfer means, the remainder of data is transferred by every one transfer unit by said second transfer means.
A control method for a DMA controller arranged to transfer data between a main storage connected to a system bus and an I/O device connected to an I/O bus through an FIFO memory arranged to buffer a difference in transfer speed between said system bus and said I/O bus, said control method comprising:
- a first transfer step of transferring data between said main storage and said FIFO memory through said system bus;
- a request receiving step of receiving from said I/O device a request for transfer by DMA;
- a second transfer step of transferring data by every one transfer unit between said FIFO memory and said I/O device through said I/O bus when a request for normal transfer by DMA is received in said request receiving step;
- and
- a third transfer step of continuously transferring data by a predetermined number of transfer units between said FIFO memory and said I/O device through said I/O bus when a request for continuous transfer by DMA is received in said request receiving step,
- wherein if a remainder of data to be transferred less than the predetermined number of transfer units during a transfer by the predetermined number of transfer units in said third transfer step, the remainder of data is transferred by every one transfer unit.
Dependencies are inferred from the claim text.