Loading patent…
AssigneeHewlett-Packard Development Company, L.P.
InventorsZheng Zhang, Sekhar R. Sarukkai
Estimating the term…
A method for operating a shared memory computer system to reduce the latency times associated with lock/unlock code sequences. The computer system includes a shared memory and a plurality of processors. When one of the processors wishes to modify a shared variable stored in the shared memory, the processor must first request and receive a lock from the shared memory. The lock prevents any other processor in the computer system from modifying data in the shared memory during the locked period. In the present invention, a list of variables in the shared memory that are shared by two or more of the processors is generated. When one of the processors is granted a lock, a prefetch instruction is executed for each variable in the list. Each prefetch instruction specifies the processor receiving the lock as the destination of the data specified in that prefetch instruction. The list may be generated by a compiler during the compilation of a program that is to run on one of the processors. Alternatively, the list can be generated while the program is running either with test data or during the normal execution of the program. The list generation and prefetch instruction executions may be carried out by modifying the program and/or shared memory controller code or via special purpose hardware that monitors the memory bus.
In a method for operating a shared memory computer system comprising a shared memory and a plurality of processors, wherein one of said processors wishing to modify a shared variable stored in said shared memory must first request and receive a lock from said shared memory, said lock preventing any other processor in said computer system from modifying data in said shared memory;
In a shared memory computer system comprising a shared memory and a plurality of processors, wherein one of said processors wishing to modify a shared variable stored in said shared memory must first request and receive a lock from said shared memory, said lock preventing any other processor in said computer system from modifying data in said shared memory, the improvement comprising a controller coupled to a bus that is shared with said shared memory, said controller recognizing said lock commands and unlock commands on said bus, said controller also recognizing cache misses on said bus, said controller generating a list of variables in said shared memory that are shared by two or more of said processors;
Dependencies are inferred from the claim text.