Setting data retention thresholds in charge-based memory

An apparatus, comprising:

• a memory including
• a plurality of addressable memory cells;
• a first reference circuit to produce a predetermined first reference value;
• and
• a first comparison circuit coupled to the plurality of memory cells and to the first reference circuit to determine if an addressed one of the plurality of memory cells is programmed to a first level greater than or a second level less than the predetermined first reference value;
• wherein the predetermined first reference value is selected to increase a predicted time-to-failure of the memory, based on an application-specific usage profile for the memory.

A system, comprising:

• a processor;
• a memory coupled to the processor and including
• a plurality of addressable memory cells;
• a first reference circuit to produce a predetermined first reference value;
• and
• a first comparison circuit coupled to the plurality of memory cells and to the first reference circuit to determine if an addressed one of the plurality of memory cells is programmed to a first level greater than or a second level less than the predetermined first reference value;
• wherein the predetermined first reference value is selected to increase a predicted time-to-failure of the memory, based on an application-specific usage profile for the memory.

A memory made with a process comprising:

• predicting a first leakage curve for a first state in the memory, based on an anticipated application-specific usage profile for the memory;
• predicting a second leakage curve for a second state in the memory, based on the anticipated application-specific usage profile for the memory;
• determining a first reference value to increase a predicted operational life of the memory, based on the first and second predicted leakage curves;
• and
• programming a first reference circuit with the first reference value.