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US 6,651,022 B2Granted
Semiconductor device capable of test mode operation
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorShunsuke Endo
Life of this patent
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Abstract
An output signal from a level detection circuit that detects a super VIH (normal logical high voltage level) condition is set to a valid state or to an invalid state by a force circuit and is applied to a test control circuit. A test mode with the super VIH (SVIH) condition can be entered efficiently, while the possibility of an erroneous entry on the user side and constraints of the test apparatus upon serial test entry are suppressed.
Claims15
A semiconductor device, comprising:
- mode detection circuitry for activating a specific mode instruction signal when a voltage of a specific node is at a first voltage;
- control signal generating circuitry for generating a control signal for activating an operation designated by an operation mode instruction signal in response to an output signal from said mode detection circuitry and said operation mode instruction signal;
- and
- force circuitry for forcing said specific mode instruction signal to either one of an activated state and an inactivated state independently of a level of the voltage of said specific node.
1 more element
A semiconductor device operable in a plurality of test modes, comprising:
- test mode detection circuitry for generating an internal signal for designating a test mode designated by a test mode instruction signal applied externally when a voltage of a specific node is at least at a prescribed voltage level;
- and
- test condition setting circuitry for selectively setting a voltage condition of said specific node to either of a valid state and an invalid state for said plurality of test modes.
Dependencies are inferred from the claim text.