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AssigneeAgere Systems Inc.
InventorsStephen T. Janesch, Carl R. Stevenson
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A digital phase locked loop (PLL) frequency synthesizer includes a 1-bit numerically controlled oscillator (NCO) to negate the requirement that a VCO frequency be an integer multiple of its reference frequency. Thus, in accordance with the principles of the present invention, a direct digital synthesizer (DDS) or numerically controlled oscillator (NCO) is used to form a frequency divider in a feedback path of a PLL. Thus, a synthesizer with fine frequency control and very fast settling time is disclosed. The conventional integer-ratio relationship between the reference frequency fREF and the synthesized output frequency signal fVCO is overcome by replacement of a conventional VCO divider in a feedback path of a digital PLL with a 1-bit NCO. This allows the reference frequency fREF to be greater than the channel spacing, i.e., the channel spacing can be smaller than the reference frequency fREF. Thus, a much quicker settling time and improved VCO phase noise are provided, either of which results in a significant improvement in the performance of virtually any communications system.
A digital phase locked loop, comprising:
A digital phase locked loop, comprising:
A method of providing feedback between an output signal of a voltage controlled oscillator and an input signal to a phase detector in a digital phase locked loop, comprising:
A method of providing feedback between an output signal of a voltage controlled oscillator and an input signal to a phase detector in a digital phase locked loop, comprising:
Apparatus for providing feedback between an output signal of a voltage controlled oscillator and an input signal to a phase detector in a digital phase locked loop, comprising:
Apparatus for providing feedback between an output signal of a voltage controlled oscillator and an input signal to a phase detector in a digital phase locked loop, comprising:
Dependencies are inferred from the claim text.