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US 6,650,720 B1Granted
Phase lock loop and transconductance circuit for clock recovery
AssigneeXilinx, Inc.
InventorsBernard L. Grung, Moises E. Robinson
Life of this patent
Estimating the term…
Abstract
A high speed data communication system includes a receiver to recover data and clock signals from communicated data. The receiver circuit has a dual phase lock loop (PLL) circuit. A fine loop of the PLL includes a phase detector providing a differential analog voltage output. Transconductance circuitry converts the differential analog voltage output to a low current analog output. The transconductance circuitry has a high impedance output, a small transconductance value and can provide variable gain control. A coarse loop of the PLL allows for frequency acquisition of an internal oscillator.
Claims30
A high speed data receiver comprising:
- a phase detector circuit coupled to receive a high speed input data signal and provide at least two analog voltage outputs;
- a transconductance circuit coupled to the phase detector circuit for converting the at least two analog voltage outputs into an analog output current, wherein the transconductance circuit includes a variable gain adjust circuit for adjusting a gain of the transconductance circuit in response to variations in a magnitude of the high speed input data signal;
- an oscillator coupled to the transconductance circuit and providing the second input signal to the phase detector in response to the analog output current;
- a phase frequency detector circuit coupled to receive an output of the oscillator and provide an output indicating a frequency difference between the output of the oscillator and a reference clock signal;
- and
- a charge pump circuit for providing an output signal in response to the phase frequency detector circuit, the charge pump output signal is coupled to an input of the oscillator.
3 more elements
A high speed data receiver comprising:
- a phase detector circuit coupled to receive a high speed input data signal and provide differential analog voltage outputs indicating a signal phase difference between the high speed input data signal and a second input signal;
- a transconductance circuit coupled to the phase detector circuit for converting the differential analog voltage outputs into an analog output current;
- an oscillator coupled to the transconductance circuit and providing the second input signal to the phase detector in response to the analog output current, wherein the oscillator comprises a second transconductance circuit configured to convert an intermediary analog voltage generated from the analog output current to an intermediary analog current and a ring oscillator configured to receive said intermediary analog current and to provide the second input signal;
- a phase frequency detector circuit coupled to receive an output of the oscillator and provide an output indicating a frequency difference between the output of the oscillator and a reference clock signal;
- and
- a charge pump circuit for providing an output signal in response to the phase frequency detector circuit, the charge pump output signal is coupled to an input of the oscillator.
3 more elements
A high output impedance, low output current transconductance circuit comprising:
- a first transistor having a gate coupled to a first differential voltage input, a drain coupled to a first supply voltage through a first resistance, and a source coupled to a second supply voltage through a first degenerative resistor;
- a second transistor having a gate coupled to a second differential voltage input, a drain coupled to the first supply voltage through a second resistance, and a source coupled to the second supply voltage through a second degenerative resistor;
- a first mirror circuit for coupling a proportionately reduced current mirror of a current through the first transistor to an output node as a pull-up current;
- and
- a second mirror circuit for coupling a proportionately reduced current mirror of a current through the second transistor to the output node as a pull-down current.
2 more elements
A data communication system comprising:
- a transmitter for transmitting high speed data on a communication line;
- and
- a receiver coupled to the communication line for receiving the high speed data and extracting a clock signal, the receiver comprises:
- a phase detector circuit coupled to receive a high speed input data signal and provide differential analog voltage outputs indicating a signal phase difference between the high speed input data signal and a second input signal;
- a transconductance circuit coupled to the phase detector circuit for converting the differential analog voltage outputs into an analog output current, wherein the transconductance circuit includes:
- a fixed transconductance circuit;
- and
- a variable transconductance circuit operably coupled to the fixed transconductance circuit to produce the analog output current;
- an oscillator coupled to the transconductance circuit and providing the second input signal to the phase detector in response to the analog output current;
- a phase frequency detector circuit coupled to receive an output of the oscillator and provide an output indicating a frequency difference between the output of the oscillator and a reference clock signal;
- and
- a charge pump circuit for providing an output signal in response to the phase frequency detector circuit, the charge pump output signal is coupled to an input of the oscillator.
9 more elements
A high speed data receiver comprising:
- a phase detector circuit coupled to receive a high speed input data signal and provide at least two analog voltage outputs;
- a transconductance circuit coupled to the phase detector circuit for converting the at least two analog voltage outputs into an analog output current, wherein the transconductance circuit includes:
- a differential input stage having first and second inputs for receiving the differential analog voltage outputs, the differential input stage having a first current path controlled by the first input, and a second current path controlled by the second input;
- and
- an output stage including:
- a first current mirror circuit for mirroring a same current provided in the first current path to a third current path,
- a second current mirror circuit for mirroring {fraction (1/10)} of the current provided in the third current path to a fourth current path;
- a third current mirror circuit for mirroring a same current provided in the fourth current path to a sixth current path, the sixth current path forms part of an output current path;
- a fourth current mirror circuit for mirroring a same current provided in the second current path to a fifth current path;
- and
- a fifth current mirror circuit for mirroring {fraction (1/10)} of the current provided in the fifth current path to the sixth current path;
- and an oscillator coupled to the transconductance circuit and providing the second input signal to the phase detector in response to the analog output current.
9 more elements
Dependencies are inferred from the claim text.