Correlator co-processor for CDMA RAKE receiver operations

A correlator co-processor (CCP) for a RAKE receiver comprising:

• means for generating pseudo-noise (PN) codes;
• means for generating Walsh codes;
• means for receiving and storing in-phase and quadrature (I/Q) sub-chip samples;
• timing means for counting chip samples received by the receiving and storing means;
• data processing means for processing samples of the PN codes, samples of the Walsh codes and the I/Q sub-chip samples;
• means for storing a plurality of programmably executable tasks;
• means for storing a plurality of configuration tables;
• means for generating interrupt signals;
• means for storing output data;
• and
• controlling means in communication with the data processing means, task storing means, configuration table storing means, interrupt generating means, PN code generating means, Walsh code generating means, timing means and output data storing means, such that the controlling means, directed by the programmably executable tasks, can direct the data processing means to process the samples of the PN codes, the samples of the Walsh codes and the I/Q sub-chip samples, and therefrom generate RAKE receiver data.

A correlator co-processor (CCP) for a RAKE receiver comprising:

• a pseudo-noise (PN) code generator having a control input and a PN code output;
• a Walsh code generator having a control input and a Walsh code output;
• at least one input buffer, each input buffer having at least one in-phase and quadrature (I/Q) signal sample input, a control input, and a complex signal output;
• at least one chip counter (GCC), each GCC having a signal sample input in communication with the at least one I/Q signal sample input and further having a local reference clock output;
• a data path having at least one output, a first data path input in communication with the PN code output and the Walsh code output, a second data path input in communication with the complex signal output, and further having a third data path input;
• at least one task buffer having an input and an output and configured to store a list of programmably executable tasks;
• at least one configuration table buffer having a first output and a second output, the first output in communication with the at least one task buffer input, and further having at least one input in communication with an external system interface bus;
• an interrupt generator having an input, a first output and a second output, the second output in communication with the external system interface bus;
• at least one output data buffer having at least one input in communication with the at least one data path output, and further having at least one output in communication with the external system interface bus;
• and
• a controller synchronized with the local reference clock output and having a first output in communication with the third data path input, a second output in communication with the PN code generator control input, the Walsh code generator control input and the input buffer control input, a third output in communication with the interrupt generator input, a first input in communication with the at least one task buffer output, and a second input in communication with the at least one configuration table second output.