System that compensates for variances due to process and temperature changes

A system comprising:

• a Receiver that receives a serial data stream;
• a multistage delay line operatively coupled to the Receiver;
• a plurality of latches with each one of the plurality of latches operatively coupled to store data output from a stage of the multistage delay line;
• a first multiplexer operatively coupled to the plurality of latches;
• a second multiplexer operatively coupled to the plurality of latches;
• a controller including a memory that receives data from the plurality of latches and a processor executing a program that monitors the data in the memory and output control signals, indicting a shift of bit position in the delay line due to temperature variations, to drive said first multiplexer and said second multiplexer.

A method of processing data in a system comprising the steps of:

• sending data through a multistage delay line;
• providing a different register to store a bit output from the multistage delay line;
• capturing, from the different register, a first group of bits;
• generating from the group of bits an Edge1 value and an Edge2 value wherein the Edge1 value and the Edge2 value represent locations of bits within the delay line;
• thereafter, sequentially capturing groups of bits and for each group of captured bits, defining a First Jitter Allowance Region about Edge1 or a preceding edge;
• defining a Second Jitter Allowance Region about Edge2 or a preceding edge value;
• calculating a new Edge1 value;
• calculating a new Edge2 value;
• adjusting the new Edge1 value and the new Edge2 value to compensate for jitter;
• and
• correlating the adjusted Edge1 value, the adjusted Edge2 value, the Edge1 value or preceding edge value and Edge2 value or preceding edge value to select a new position in the delay line whereat bits are repositioned due to temperature variation.