Data processing system, method, and product for automatically performing timing checks on a memory cell using a static timing tool
AssigneeInternational Business Machines Corporation
InventorsMatthew J. Amatangelo, Christopher M. Durham, Peter Juergen Klim
Life of this patent
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Abstract
A system, method, and computer program product are disclosed for automatically performing timing checks on a memory cell. A static timing tool is provided that includes multiple, different standard timing elements. Each standard timing element is associated with one or more standard timing checks. The memory cell is represented using one or more of the standard timing elements. Standard timing checks associated with the timing elements used to represent the memory cell are used to verify timing in the memory cell.
Claims27
A method in a data processing system for automatically performing timing checks on a memory cell, said method comprising the steps of:
- providing a static timing tool, said timing tool including a plurality of different standard timing checks;
- and
- utilizing said plurality of standard timing checks to verify read timing and write timing in said memory cell;
- determining whether a read operation timing in said memory cell is to be verified;
- in response to a determination that a read operation timing in said memory cell is to be verified, executing a read setup timing check to determine whether data in said memory cell has reached a predetermined voltage level prior to a read enable event;
- and
- only in response to a determination that said memory cell passed said read timing check, utilizing said plurality of standard timing checks to verify timing in said memory cell.
A data processing system for automatically performing timing checks on a memory cell, said data processing system comprising:
- a static timing tool, said static timing tool including a plurality of different standard timing checks;
- means for utilizing said plurality of standard timing checks to verify read timing and write timing in said memory cell;
- means for determining whether a read operation timing in said memory cells is to be verified;
- in response to a determination that a road operation timing said memory cell is to be verified, means executing a read setup timing check to determine whether data in said memory cell has reached a predetermined voltage level prior to a read enable event;
- and
- only in response to a determination that said memory cell passed said read timing check, means for utilizing said plurality of standard timing checks to verify timing in said memory cell.
A computer program product in a data processing system for automatically performing timing checks on a memory cell, said computer program product comprising:
- instruction means for providing a static timing tool, said timing tool including a plurality of different standard timing checks;
- and
- instruction means for utilizing said plurality of standard timing checks to verify read timing and write timing in said memory cell;
- instruction means for determination whether a read operation timing in said memory cell is to be verified;
- in response to a determination that a read operation timing in said memory cell is to be verified, instruction means for executing a read setup timing check to determine whether data in said memory cell has reached a predetermined voltage level prior to a read enable event;
- and
- only in response to a determination that said memory cell passed said read timing check, instruction means for utilizing said plurality of standard timing checks to verify timing in said memory cell.
Dependencies are inferred from the claim text.