Nonvolatile semiconductor memory device
AssigneeSeiko Epson Corporation
InventorYoshihito Owa
Life of this patent
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Abstract
A nonvolatile semiconductor memory device has a plurality of memory cells arranged in first and second directions, each of the memory cells having two MONOS memory cells controlled by one word gate and two control gates. A memory cell array region has a plurality of control gate lines formed by connecting, in the first direction, control gates of the memory cells in each column arranged in the first direction, and sub control gate lines extending in the first direction in an upper layer of the plurality of control gate lines, the number of the sub control gate lines being half the number of the control gate lines. Each two control gate lines adjacent across the boundaries between the plurality of memory cells in the second direction are connected in common with one sub control gate line.
Claims16
A nonvolatile semiconductor memory device comprising:
- a memory cell array region in which a plurality of memory cells are arranged in first and second directions intersecting each other, each of the memory cells having two nonvolatile memory elements and being controlled by one word gate and two control gates;
- and
- wherein the memory cell array region includes:
- a plurality of control gate lines formed by connecting, in the first direction, each of the control gates of the memory cells in each column arranged in the first direction;
- and
- sub-control gate lines extending in the first direction in an upper layer of the control gate lines, the number of the sub-control gate lines being half the number of the control gate lines, and
- wherein each two control gate lines adjacent across the boundaries between the memory cells arranged in the second direction are connected in common with one sub-control gate line.
A nonvolatile semiconductor memory device comprising:
- a memory cell array region in which a plurality of memory cells are arranged in first and second directions intersecting each other, each of the memory cells having two nonvolatile memory elements and being controlled by one word gate and two control gates, and
- wherein the memory cell array region comprises:
- a plurality of bit lines formed of impurity layers extending in the first direction, the bit lines are disposed on both sides of the memory cells arranged in the first direction;
- a plurality of control gate lines formed by connecting, in the first direction, each of the control gates of the memory cells in each column arranged in the first direction, the number of control gate lines being twice the number of the bit lines;
- sub-control gate lines extending in the first direction in an upper layer of the plurality of control gate lines, the number of sub-control gate lines being the same as the number of the bit lines;
- and
- a plurality of word lines extending in the second direction,
- wherein each two control gate lines adjacent across the boundaries between the memory cells arranged in the second direction are connected in common with one sub-control gate line.
Dependencies are inferred from the claim text.