Semiconductor memory device with reduced its chip area and power consumption

A semiconductor memory device comprising:

• a plurality of first word lines each connected to a plurality of memory cells;
• a first word-line-driving circuit connected to the first word lines to drive the first word lines;
• a second word line connected to the first word-line-driving circuit;
• a second word-line-driving circuit connected to the second word line;
• a first address signal supplied to the second word-drive-line driving circuit;
• a first word drive line connected to the first word-line-driving circuit;
• a second word drive line connected to the first word-line-driving circuit and complementary to the first word drive line;
• a first word-drive-line-driving circuit connected to the first and second word drive lines to drive the first and second word drive lines;
• a third word drive line connected to the first word-drive-line driving circuit;
• a second word-drive-line-driving circuit connected to the third word drive line to drive the third word drive line;
• a second address signal supplied to the second word-drive-line-driving circuit;
• a block select line connected to the first word-drive-line-driving circuit;
• a block-select-line-driving circuit connected to the block select line to drive the block select line;
• and
• a third address signal supplied to the block-select-line-driving circuit,
• wherein:
• the second word-drive-line-driving circuit generates a first signal in accordance with the second address signal to thereby drive the third word drive line, the second address signal having high and low levels set at first and second voltages, respectively, the first signal having high and low levels set at the first voltage and a third voltage lower than the second voltage, respectively;
• the block-select-line-driving circuit generates a second signal in accordance with the third address signal to thereby drive the block select line, the third address signal having high and low levels set at the first voltage and the second voltage, respectively, the second signal having high and low levels set at a fourth voltage higher than the first voltage and the third voltage, respectively;
• the first word-drive-line driving circuit generates third and fourth signals in accordance with the first signal supplied from the second word-drive-line-driving circuit via the third word drive line, and a level of the second signal supplied from the block-select-line-driving circuit via the block select line, thereby driving the first and second word drive lines, the third signal having high and low levels set at the fourth voltage and the third voltage, respectively, the fourth signal having high and low levels set at the first and third voltages, respectively;
• the second word-line-driving circuit generates a fifth signal in accordance with the first address signal to thereby drive the second word line, the first address signal having high and low levels set at the first and second voltages, respectively, the fifth signal having high and low levels set at the fourth and third voltages, respectively;
• and
• the first word-line-driving circuit generates a sixth signal in accordance with the third and fourth signals supplied from the first and second word drive lines, and the fifth signal supplied from the second word-line-driving circuit via the second word line, thereby driving the first word lines, the sixth signal having high and low levels set at the fourth voltage and the third voltage, respectively.

A semiconductor memory device comprising:

• a plurality of first word lines connected to a plurality of memory cells;
• a plurality of first word-line-driving circuits connected to the respective first word lines;
• a second word line connected to the first word-line-driving circuits;
• a second word-line-driving circuit connected to the first word-line-driving circuits, and configured to drive the second word line in accordance with a first address signal;
• a plurality of first and second word drive lines connected to the first word-line-driving circuits;
• a plurality of first word-drive-line-driving circuits connected to the first and second word drive lines;
• a third word drive line connected to the first word-drive-line-driving circuits;
• a second word-drive-line-driving circuit connected to the third word drive line and configured to drive the third word drive line in accordance with a second address signal;
• and
• a block-select-line-driving circuit connected to the first word-drive-line-driving circuits and configured to drive the block select line in accordance with a third address signal,
• wherein:
• the second word-drive-line-driving circuit generates a first signal in accordance with the second address signal to thereby drive the third word drive line, the second address signal having high and low levels set at first and second voltages, respectively, the first signal having high and low levels set at the first voltage and a third voltage lower than the second voltage, respectively;
• the block-select-line-driving circuit generates a second signal in accordance with the third address signal to thereby drive the block select line, the third address signal having high and low levels set at the first and second voltages, respectively, the second signal having high and low levels set at a fourth voltage higher than the first voltage and the third voltage, respectively;
• each of the first word-drive-line-driving circuits generates third and fourth signals in accordance with the first signal supplied from the second word-drive-line-driving circuit via the third word drive line, and a level of the second signal supplied from the block-select-line-driving circuit via the block select line, thereby driving the first and second word drive lines, the third signal having high and low levels set at the fourth voltage and the third voltage, respectively, the fourth signal having high and low levels set at the first and third voltages, respectively;
• the second word-line-driving circuit generates a fifth signal in accordance with the first address signal to thereby drive the second word line, the first address signal having high and low levels set at the first and second voltages, respectively, the fifth signal having high and low levels set at the fourth and third voltages, respectively;
• and
• each of the first word-line-driving circuits generates a sixth signal in accordance with the third and fourth signals supplied from the first and second word drive lines, and the fifth signal supplied from the second word-line-driving circuit via the second word line, thereby driving the first word lines, the sixth signal having high and low levels set at the fourth voltage and the third voltage, respectively.