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US 6,650,589 B2Granted
Low voltage operation of static random access memory
AssigneeIntel Corporation
InventorLawrence T. Clark
Life of this patent
Estimating the term…
Abstract
An integrated circuit having a microprocessor core and a memory block that may operate at different voltages. A voltage regulator, either external to the integrated circuit or designed as part of the integrated circuit, generates the two voltages. The operating voltage for the microprocessor core is selected to satisfy power and performance criteria while the operating voltage for the memory block is set to provide acceptable noise margins and maintain stability of the memory cells within the memory block.
Claims21
A system comprising:
- a logic core to receive a first operating voltage potential;
- a Static Random Access Memory (SRAM) block integrated with the logic core to receive a second operating voltage potential that differs from the first operating voltage potential;
- and
- a translator block to receive the first and second operating voltage potentials and adjust signals received from the logic core having the first operating voltage potential to provide signals to the SRAM block at the second operating voltage potential.
1 more element
A device, comprising:
- a Static Random Access Memory (SRAM) core embedded on the device;
- and
- a microprocessor coupled to the SRAM core, where the microprocessor operates at a first voltage and the SRAM core operates at a second voltage.
An apparatus, comprising:
- a processing core coupled to receive a first operating voltage;
- a translator block coupled to receive the first operating voltage and a second operating voltage;
- and
- an embedded memory block having a memory core and sense amps, where the memory core is coupled to receive the second operating voltage and the sense amps are coupled to receive the first operating voltage and the second operating voltage.
1 more element
A method, comprising:
- operating a processing core at a first voltage;
- and
- operating a Static Random Access Memory (SRAM) block at a second voltage that differs from the first voltage, the SRAM block being coupled to the processing core.
Dependencies are inferred from the claim text.