Semiconductor memory module and register buffer device for use in the same
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTadato Yamagata
Life of this patent
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Abstract
In a semiconductor memory module having a plurality of DRAMs, when an input command is detected as a refresh command according to external control signals externally input for command-execution to a register buffer, internal control signals for a partial number of the DRAMs preliminarily selected among the plurality of DRAMs are delayed. Thus, the refresh command is executed with a time difference, and the semiconductor memory module prevents the plurality of dynamic semiconductor memories from simultaneously entering refresh modes to cause a great peak current to flow, and thereby implementing a stable operation.
Claims13
A semiconductor memory module which is provided with a plurality of dynamic semiconductor memories, and which generates internal control signals as a command to be applied to the plurality of individual dynamic semiconductor memories according to external control signals externally input to thereby execute the command, the semiconductor memory module comprising:
- mode determining means for determining whether or not the command is a refresh command in a refresh mode according to the internal control signals;
- and
- delay means for establishing a delay in applying the internal control signals to a partial number of dynamic semiconductor memories preliminarily selected among the plurality of dynamic semiconductor memories,
- whereby the refresh command is transferred to the plurality of dynamic semiconductor memories with a time difference according to the delay in the refresh mode.
A register buffer device used in a semiconductor memory module having a plurality of dynamic semiconductor memories mounted thereon, the register buffer device comprising:
- means for generating internal control signals for executing a command for the plurality of individual dynamic semiconductor memories according to external control signals externally input to the register buffer device;
- mode determining means for determining whether or not the command is a refresh command in a refresh mode according to the external control signals;
- and
- delay means for establishing a delay in the internal control signals to be supplied to a partial number of dynamic semiconductor memories preliminarily selected among the plurality of dynamic semiconductor memories,
- whereby the refresh command is transferred to the plurality of dynamic semiconductor memories with a time difference according to the delay in the refresh mode.
A register buffer device used in a semiconductor memory module having a plurality of dynamic semiconductor memories mounted thereon, the register buffer device comprising control means for performing control operations of:
- generating internal control signals for executing a command for the plurality of individual dynamic semiconductor memories according to external control signals externally input to the register buffer device;
- determining whether or not the command is a refresh command in a refresh mode according to the external control signals;
- and
- establishing a delay in the internal control signals to be supplied to a partial number of dynamic semiconductor memories preliminarily selected among the plurality of dynamic semiconductor memories,
- whereby the refresh command is transferred to the plurality of dynamic semiconductor memories with a time difference according to the delay in the refresh mode.
Dependencies are inferred from the claim text.