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US 6,650,587 B2Granted
Partial array self-refresh
AssigneeMicron Technology, Inc.
InventorsScott J. Derner, Casey R. Kurth, Daryl L. Habersetzer
Life of this patent
Estimating the term…
Abstract
A memory device includes an address selection circuit to store addresses of selected rows of memory cells. During a refresh mode, only the memory cells of the selected rows are refreshed. The addresses of the selected rows can be stored by a user or automatically.
Claims49
A memory device comprising:
- a counter to count addresses of rows of memory cells;
- a register including a plurality of register cells for storing selected addresses of rows of memory cells;
- and
- a compare circuit including a plurality of compare units connected to the counter and the register to compare an address counted by the counter with the selected addresses such that a row of memory cells located at the address counted by the counter is refreshed if the address counted by the counter is within the selected addresses.
1 more element
A memory device comprising:
- a counter to count addresses of rows of memory cells;
- a register to store selected addresses of rows of memory cells;
- and
- a compare circuit connected to the counter and the register to compare an address counted by the counter with the selected addresses such that a row of memory cells located at the address counted by the counter is refreshed if the address counted by the counter is within the selected addresses, wherein the memory device further comprises:
- a number of counter bit lines connected to the counter;
- a number of register bit lines connected to the register;
- and a number of compare units, wherein each of the compare units connects to one counter bit line and one register bit line.
4 more elements
A memory device comprising:
- a counter to count addresses of rows of memory cells;
- a register to store selected addresses of rows of memory cells;
- and
- a compare circuit connected to the counter and the register to compare an address counted by the counter with the selected addresses such that a row of memory cells located at the address counted by the counter is refreshed if the address counted by the counter is within the selected addresses, wherein the memory device further comprises:
- a number of counter bit lines connected to the counter;
- a number of register bit lines connected to the register;
- and a number of compare units, and wherein each of the compare units connects one register bit line and a subset of counter bit lines.
4 more elements
A memory device comprising:
- a counter to count addresses of rows of memory cells;
- a register to store selected addresses of rows of memory cells;
- and
- a compare circuit connected to the counter and the register to compare an address counted by the counter with the selected addresses such that a row of memory cells located at the address counted by the counter is refreshed if the address counted by the counter is within the selected addresses, wherein the register includes a number of storage elements to store a number of the data bits, wherein a combination of the data bits represents the selected addresses of rows of memory cells.
1 more element
A memory device comprising:
- a counter to count addresses of rows of memory cells;
- a register to store selected addresses of rows of memory cells;
- and
- a compare circuit connected to the counter and the register to compare an address counted by the counter with the selected addresses such that a row of memory cells located at the address counted by the counter is refreshed if the address counted by the counter is within the selected addresses, wherein the register includes a number of register cells to store a number of data bits, wherein one of the data bits represents the selected addresses of rows of memory cells.
1 more element
A memory device comprising:
- a counter including a plurality of counter bit lines to generate a plurality of count signals, each combination of the count signals representing a unique address of a row of memory cells;
- a plurality of storage elements, configured to be programmed to form a combination of data bits that represents a plurality of rows of selected addresses of memory cells;
- and
- a plurality of compare units, each of the compare units being connected to one counter bit line and to one of the storage elements for comparing an address generated by the counter with the selected addresses such that a row of memory cells located at the address generated by the counter is refreshed when the address generated by the counter is within the selected addresses.
1 more element
A memory device comprising:
- a counter including a plurality of counter bit lines to generate a plurality of count signals, each combination of the count signals representing an address of a row of memory cells;
- a plurality of storage elements to represents a plurality of ranges of addresses, each of the storage elements being configured to be programmed to represent a selected range of addresses;
- and
- a plurality of compare units, each of the compare units being connected to a subset of the counter bit lines and one of the storage elements to compare an address generated by the counter with the range of addresses such that a row of memory cells located at the address generated by the counter is refreshed when the address generated by the counter is within the selected range of addresses.
1 more element
A memory device comprising:
- a counter including a first and a second group of counter bit lines to generate a plurality of count signals, each combination of the count signals representing an address of a row of memory cells;
- a first register to store selected addresses represented by the first group of counter bit lines;
- a first compare circuit connected to the first register and the first group of the counter bit lines to compare an address counted by the counter with the selected addresses stored in the first register;
- a second register to store selected addresses represented by the second group of counter bit lines;
- a second compare circuit connected to the second register and the second group of the counter bit lines to compare the address counted by the counter with the selected addresses stored in the second register;
- and
- a combinatorial circuit connected to the first and second compare circuits to provide a refresh address select signal to refresh memory cells located at the address counted by the counter if the address counted by the counter matches the selected address stored in the first or the second register.
4 more elements
A memory device comprising:
- a counter including a plurality of counter bit lines to generate a plurality of count signals, each combination of the count signals representing a unique address of a row of memory cells;
- a first register to store selected addresses of a row of memory cells;
- a first compare connected to the first register and the counter bit lines to compare an address counted by the counter with the selected addresses stored in the first register;
- a second register to store selected addresses of a row of memory cells;
- a second compare circuit connected to the second register and a subset of counter bit lines to compare the address counted by the counter with the selected addresses stored in the second register;
- and
- a selector connected to the first and second compare circuits to provide a refresh address select signal based on a select signal to refresh memory cells located at the address counted by the counter if the address counted by the counter matches the selected address stored in the first or the second register.
4 more elements
A memory device comprising:
- a plurality of rows of memory cells;
- a plurality of input to receive a plurality of input signals;
- a control logic to generate a refresh command signal based on certain combinations of the input signals to initiate a refresh operation;
- a counter to sequentially count addresses of the rows of memory cells in response to the refresh signal;
- a register to store selected addresses of the rows of memory cells;
- and
- a compare circuit connected to the counter and the register to compare an addresses counted by the counter with the selected addresses such that a row of memory cells located at the address counted by the counter is refreshed when the address counted by the counter is within the selected addresses.
4 more elements
A system comprising:
- a processor;
- and
- a memory device connected to the processor, the memory device comprising:
- a counter to count addresses of rows of memory cells;
- a register including a plurality of register cells for storing selected addresses of rows of memory cells;
- and
- a compare circuit including a plurality of compare units connected to the counter and the register to compare an address counted by the counter with the selected addresses such that a row of memory cells located at the address counted by the counter is refreshed when the address counted by the counter is within the selected addresses.
4 more elements
A system comprising:
- a processor and
- a memory device connected to the processor, the memory device comprising:
- a counter to count addresses of rows of memory cells;
- a register to store selected addresses of rows of memory cells;
- and
- a compare circuit connected to the counter and the register to compare an address counted by the counter with the selected addresses such that a row of memory cells located at the address counted by the counter is refreshed when the address counted by the counter is within the selected addresses, wherein the memory device further comprises:
- a number of counter bit lines connected to the counter;
- a number of number of register bit lines connected to the register;
- and a number of compare units, wherein each of the compare units connects to one counter bit line and one register bit line.
6 more elements
A system comprising:
- a processor;
- and
- a memory device connected to the processor, the memory device comprising:
- a counter to count addresses of rows of memory cells;
- a register to store selected addresses of rows of memory cells;
- and
- a compare circuit connected to the counter and the register to compare an address counted by the counter with the selected addresses such that a row of memory cells located at the address counted by the counter is refreshed when the address counted by the counter is within the selected addresses, wherein the memory device further comprises:
- a number of counter bit lines connected to the counter;
- a number of register bit lines connected to the register;
- and a number of compare units, wherein each of the compare units connects one register bit line and a subset of counter bit lines.
7 more elements
A system comprising:
- a processor;
- and
- a memory device connected to the processor, the memory device comprising:
- a counter including a first and a second group of counter bit lines to generate a plurality of count signals, each combination of the count signals representing an address of a row of memory cells;
- a first register to store selected addresses represented by the first group of counter bit lines;
- a first compare circuit connected to the first register and the first group of the counter bit lines to compare an address counted by the counter with the selected addresses stored in the first register;
- a second register to store selected addresses represented by the second group of counter bit lines;
- a second compare circuit connected to the second register and the second group of the counter bit lines to compare the address counted by the counter with the selected addresses stored in the second register;
- and
- a combinatorial circuit connected to the first and second compare circuits to provide a refresh address select signal to refresh memory cells located at the address counted by the counter if the address counted by the counter matches the selected address stored in the first or the second register.
7 more elements
A system comprising:
- a processor;
- and
- a memory device connected to the processor, the memory device comprising:
- a plurality of rows of memory cells;
- a plurality of input to receives a plurality of input signals;
- a control logic to generate a refresh command signal based on certain combination of the input signals to initiate a refresh operation;
- a counter to sequentially count addresses of the rows of memory cells in response to the refresh signal;
- a register to store selected addresses of the rows of memory cells;
- and
- a compare circuit connected to the counter and the register to compare an addresses counted by the counter with the selected addresses such that a row of memory cells located at the address counted by the counter is refreshed when the address counted by the counter is within the selected addresses.
7 more elements
A method of refreshing memory cells of a memory device, the method comprising:
- generating a count that represents an address of a row of the memory cells;
- comparing a bit of the address represented by the count with a bit of a selected address;
- and
- refreshing memory cells of a row located at the address counted by the count when the address represented by the count matches the selected address.
1 more element
A method of refreshing memory cells of a memory device, the method comprising:
- generating a count that represents an address of a row of the memory cells;
- comparing the address represented by the count with a selected address;
- and
- refreshing memory cells of a row located at the address counted by the count when the address represented by the count matches the selected address, wherein comparing includes comparing each bit of the count with a corresponding bit of a register that stores the selected address.
1 more element
A method of refreshing memory cells of a memory device, the method comprising:
- generating a count that represents an address of a row of the memory cells;
- comparing the address represented by the count with a selected address;
- and
- refreshing memory cells of a row located at the address counted by the count when the address represented by the count matches the selected address, wherein comparing includes comparing selected bits of the count with all bits of a register, wherein each bit of the register represents a range of addresses.
1 more element
A method of refreshing memory cells of a memory device, the method comprising:
- storing a plurality of stored data bits that presents selected addresses of rows of the memory cells;
- generating a plurality of counts, the counts representing addresses of a plurality of rows of memory cells;
- comparing each of the counts with the stored data bits;
- and
- refreshing memory cells of a row located at an address represented by one of the count when the address represented by one of the count matches the selected addresses.
2 more elements
Dependencies are inferred from the claim text.