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US 6,650,586 B1Granted
Circuit and system for DRAM refresh with scoreboard methodology
AssigneeIntel Corporation
InventorBlaise B. Fanning
Life of this patent
Estimating the term…
Abstract
A circuit comprising a first register and a second register to store the first and second status of the plurality of memory banks. Also, the circuit comprises a logic and an encoder circuit. The logic is coupled to the first and second registers and generates a third status of the plurality of memory banks based on the first and second status. The encoder coupled to the logic generates a refresh request in response to the third status of the plurality of memory banks.
Claims26
An integrated circuit, comprising:
- a first register to store a first statuses of a plurality of memory banks to indicate which memory banks are closed;
- a second register to store a second statuses of the plurality of memory banks to indicate which memory banks need to be refreshed;
- and
- a logic circuit coupled to the first register and the second register to generate a third statuses of the plurality of memory banks, wherein the third statuses is not based on a memory access status of another memory bank.
1 more element
A system comprising:
- a chipset;
- a processor coupled to the chipset;
- a memory device coupled to the chipset and processor, the memory device comprising a plurality of memory cells organized in a plurality of memory banks;
- a circuit coupled to the memory device comprising:
- a first register to store a first status bit for each one of a plurality of memory banks to indicate whether the memory bank is closed;
- a second register to store a second status bit for each one of the plurality of memory banks to indicate whether the memory bank needs to be refreshed;
- and;
- a logic to generate a refresh packet for a refresh request in response to the first status bit and second status bit of at least one of the plurality of memory banks.
5 more elements
A processor comprising:
- a logic unit;
- a memory device coupled to the logic unit;
- the memory device comprising a plurality of memory banks;
- a circuit coupled to the memory device, and comprising:
- a first register to store a first status bit for each one of a plurality of memory banks to indicate whether the memory bank is closed;
- a second register to store a second status bit for each one of the plurality of memory banks to indicate whether the memory bank needs to be refreshed;
- a logic coupled to the first register and second register;
- and
- a third register coupled to the logic, to generate a refresh packet for a refresh request in response to the first status bit and second status bit of at least one of the plurality of memory banks.
6 more elements
A method comprising:
- storing a first status bit for each one of a plurality of memory banks to indicate whether the memory bank is closed;
- storing a second status bit for each one of the plurality of memory banks to indicate whether memory bank needs to be refreshed;
- generating a third status for at least one of the plurality of memory banks;
- and
- generating a refresh packet for a refresh request in response to the third status.
2 more elements
Dependencies are inferred from the claim text.