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US 6,650,584 B2Granted
Full stress open digit line memory device
AssigneeMicron Technology, Inc.
InventorTimothy B. Cowles
Life of this patent
Estimating the term…
Abstract
An open digit line memory device includes a memory array. The memory array includes a plurality of memory cells. The memory cells are grouped into sub-arrays. Each of the sub-arrays includes a plurality of digit lines. The digit lines from adjacent sub-arrays connect to a plurality of sense amplifiers. The sense amplifiers located next to the edges of the memory array connect to dummy digit lines. The dummy digit lines are connected to a fixed voltage during a normal mode. During a test mode, the fixed voltage is replaced by a variable voltage so that the all of the sub-arrays, including the sub-arrays at the edges, can be equally stressed during the test mode.
Claims71
A memory device comprising:
- a memory cell connected to a first digit line;
- a sense amplifier connected to the first digit line;
- a second digit line connected to the sense amplifier, the second and first digit lines being connected to a fixed voltage during a normal mode;
- and
- a voltage controller connected to the second digit line for selectively replacing the fixed voltage with a variable voltage during a test mode.
2 more elements
A memory device comprising:
- a memory cell connected to a first digit line;
- a sense amplifier connected to the first digit line;
- a second digit line connected to the seine amplifier, the second and first digit lines being connected to a first voltage during a normal mode;
- and
- a voltage controller connected to the second digit line for selectively replacing the first voltage with a second voltage and with a third voltage during a test mode, wherein the first voltage, the second voltage, and the third voltage are unequal.
2 more elements
A memory device comprising:
- a memory cell connected to a first digit line;
- a sense amplifier connected to the first digit line;
- a second digit line connected to the sense amplifier, the second and first digit lines being connected to a first voltage during a normal mode;
- and
- a voltage controller connected to the second digit line for selectively replacing the first voltage with a second voltage and with a third voltage during a test mode, wherein the first voltage, the second voltage, and the third voltage are unequal, wherein the first digit line is located at an edge of the memory device.
2 more elements
A memory device comprising:
- a memory cell connected to a first digit line;
- a sense amplifier connected to the first digit line;
- a second digit line connected to the sense amplifier, the second and first digit lines being connected to a fixed voltage during a first mode;
- and
- a voltage controller connected to the second digit line to replace the fixed voltage with a supply voltage greater than the fixed voltage during a second mode.
2 more elements
A memory device comprising:
- a memory cell connected to a first digit line;
- a sense amplifier connected to the first digit line;
- a second digit line connected to the sense amplifier, the second and first digit lines being connected to a fixed voltage during a first mode;
- and
- a voltage controller connected to the second digit line to replace the fixed voltage with ground potential during a second mode.
2 more elements
A memory device comprising:
- a memory cell connected to a first digit line;
- a sense amplifier connected to the first digit line;
- a second digit line connected to the sense amplifier, the second and first digit lines being connected to a fixed voltage during a first mode;
- and
- a voltage controller connected to the second digit line to replace the fixed voltage with ground potential during a second mode, wherein the first digit line connects to memory cells located at an edge of the memory device.
2 more elements
A memory device comprising:
- a sub-array having a number of dummy digit lines;
- a number of sense amplifiers connected to the dummy digit lines, the dummy digit lines being connected to a fixed voltage during a normal mode;
- and
- a voltage controller connected to the dummy digit lines to replace the fixed voltage with a variable voltage during a test mode.
1 more element
A memory device comprising:
- a sub-array having a number of dummy digit lines;
- a number of sense amplifiers connected to the dummy digit lines, the dummy digit lines being connected to a fixed voltage during a normal mode;
- and
- a voltage controller connected to the dummy digit lines to replace the fixed voltage with a variable voltage during a test mode, wherein the fixed voltage equals one-half of the supply voltage.
1 more element
A memory device comprising:
- a sub-array having a number of dummy digit lines;
- a number of sense amplifiers connected to the dummy digit lines, the dummy digit lines being connected to a fixed voltage during a normal mode;
- and
- a voltage controller connected to the dummy digit lines to replace the fixed voltage with a variable voltage during a test mode, wherein the variable voltage is greater than the fixed voltage.
1 more element
A memory device comprising:
- a sub-array having a number of dummy digit lines;
- a number of sense amplifiers connected to the dummy digit lines, the dummy digit lines being connected to a fixed voltage during a normal mode;
- and
- a voltage controller connected to the dummy digit lines to replace the fixed voltage with a variable voltage during a test mode, wherein the variable voltage is smaller than the fixed voltage.
1 more element
A memory device comprising:
- a sub-array having a number of dummy digit lines;
- a number of sense amplifiers connected to the dummy digit lines, the dummy digit lines being connected to a fixed voltage during a normal mode;
- and
- a voltage controller connected to the dummy digit lines to replace the fixed voltage with a variable voltage during a test mode, wherein the sense amplifier and the dummy digit lines are located at an edge of the sub-array.
1 more element
A memory device comprising:
- a sub-array having a number of dummy digit lines;
- a number of sense amplifiers connected to the dummy digit lines, the dummy digit lines being connected to a first voltage during a normal mode;
- and
- a voltage controller connected to the dummy digit lines for replacing the first voltage with a second voltage during a first mode, and for replacing the first voltage with a third voltage during a second mode, wherein the first voltage, the second voltage, and the third voltage are unequal.
1 more element
A memory device comprising:
- a memory array including a number of sub-arrays of memory cells, the sub-arrays being arranged in a row, the row running between a first edge and a second edge of the memory array, the memory cells being connected to a number of digit lines;
- a sense amplifier connected to a digit line of the sub-array located next to the first edge for connecting the digit line to a fixed voltage during a normal mode;
- and
- a voltage controller connected to the sense amplifier and the digit line for replacing the fixed voltage with a variable voltage during a test mode.
1 more element
A memory device comprising:
- a memory array including a number of sub-arrays of memory cells, the sub-arrays being arranged in a row, the row running between a first edge and a second edge of the memory array, the memory cells being connected to a number of digit lines;
- a sense amplifier connected to a digit line of the sub-array located next to the first edge for connecting the digit line to a fixed voltage during a normal mode;
- and
- a voltage controller connected to the sense amplifier and the digit line for replacing the fixed voltage with a variable voltage during a test mode, wherein the fixed voltage equals one-half of the supply voltage.
1 more element
A memory device comprising:
- a memory array including a number of sub-arrays of memory cells, the sub-arrays being arranged in a row, the row running between a first edge and a second edge of the memory array, the memory cells being connected to a number of digit lines;
- a sense amplifier connected to a digit line of the sub-array located next to the first edge for connecting the digit line to a fixed voltage during a normal mode;
- and
- a voltage controller connected to the sense amplifier and the digit line for replacing the fixed voltage with a variable voltage during a test mode, wherein the variable voltage is greater than the fixed voltage.
1 more element
A memory device comprising:
- a memory array including a number of sub-arrays of memory cells, the sub-arrays being arranged in a row, the row running between a first edge and a second edge of the memory array, the memory cells being connected to a number of digit lines;
- a sense amplifier connected to a digit line of the sub-array located next to the first edge for connecting the digit line to a fixed voltage during a normal mode;
- and
- a voltage controller connected to the sense amplifier and the digit line for replacing the fixed voltage with a variable voltage during a test mode, wherein the variable smaller voltage is than the fixed voltage.
1 more element
A memory device comprising:
- a memory array including a number of sub-arrays of memory cells, the sub-arrays being arranged in a row running between a first edge and a second edge of the memory array, the memory cells being connected to a number of digit lines;
- a sense amplifier connected to a corresponding digit line of the sub-array located next to the first edge for connecting the corresponding digit line to a first voltage during a normal mode;
- and
- a voltage controller connected to the digit line for replacing the first voltage with a second voltage during a test mode, and replacing the first voltage with a third during test mode, wherein the first voltage, the second voltage, and third voltage are unequal.
1 more element
A memory device comprising:
- a number of normal memory cells and dummy memory cells;
- a number of normal digit lines connected to the normal memory cells, wherein each of the normal digit lines is configured to be driven to a supply voltage and a ground potential;
- a number of normal sense amplifiers, each connecting two normal bit lines;
- a number of dummy digit lines connected to the dummy memory cells, the dummy digit lines being connected to a fixed voltage during a normal mode;
- a number of dummy sense amplifiers, each connecting two dummy bit lines;
- a number of word lines connected to the normal and dummy memory cells for activating the normal memory cell during a normal operation;
- and
- a voltage controller connected to the dummy digit lines for replacing the fixed voltage with a variable voltage during a test mode.
5 more elements
A system comprising:
- a processor;
- and
- a memory device connected to the processor, the memory device including:
- a memory cell connected to a first digit line;
- a sense amplifier connected to the first digit line;
- a second digit line connected to the sense amplifier, the second and first digit lines being connected to a fixed voltage during a normal mode;
- and
- a voltage controller connected to the second digit line to selectively replace the fixed voltage with a variable voltage during a test mode.
5 more elements
A system comprising:
- a processor;
- and
- a memory device connected to the processor, the memory device including:
- a memory cell connected to a first digit line;
- a sense amplifier connected to the first digit line;
- a second digit line connected to the sense amplifier, the second and first digit lines being connected to a fixed voltage during a normal mode;
- and
- a voltage controller connected to the second digit line to selectively replace the fixed voltage with a variable voltage during a test mode, wherein the voltage controller includes a test voltage generator connected to the second digit line for generating a first voltage in response to a first test signal and for generating a second voltage in response to a second test signal.
5 more elements
A system comprising:
- a processor;
- and
- a memory device connected to the processor, the memory device including:
- a memory cell connected to a first digit line;
- a sense amplifier connected to the first digit line;
- a second digit line connected to the sense amplifier, the second and first digit lines being connected to a first voltage during a normal mode;
- and
- a voltage controller connected to the second digit line for selectively replacing the fixed voltage with a second voltage and with a third voltage during a test mode, wherein the first voltage, the second voltage, and the third voltage are unequal.
5 more elements
A method of testing a memory device comprising:
- activating a test mode signal during a test;
- disconnecting a fixed voltage connected to a first digit line and a second digit line connected to a sense amplifier during the test;
- and
- applying a variable voltage to the first and second digit lines during the test.
1 more element
A machine-readable medium having instructions stored thereon for causing a tester to perform a method of testing a memory device, the method comprising:
- activating a test mode signal during a test;
- disconnecting a fixed voltage connected to a first digit line and a second digit line connected to a sense amplifier during the test;
- and
- applying a variable voltage to the first and second digit lines during the test.
1 more element
Dependencies are inferred from the claim text.