Test circuit device capable of identifying error in stored data at memory cell level and semiconductor integrated circuit device including the same

A semiconductor integrated circuit device comprising:

• a memory array having a plurality of memory cells arranged in rows and columns;
• a reading circuit for generating internal read data in accordance with data of a selected memory cell in said memory array;
• a register for storing test expected value data indicative of an expected value of said internal read data;
• a determination circuit for determining whether said internal read data coincides in logic level with said test expected value data;
• a cell expected value data generating circuit for selectively inverting said test expected value data in accordance with a position, in the memory array, of said selected memory cell and generating cell expected value data;
• a modifying circuit for modifying said cell expected value data in accordance with a failure mode instruction signal designating a failure mode to be detected;
• and
• a cell level determining circuit for generating a cell level determination result signal indicating whether said selected memory cell is defective in accordance with an output signal of said modifying circuit and an output signal of said determination circuit.

A test circuit device for determining whether a memory cell in a selected address in a memory array having a plurality of memory cells is defective, comprising:

• a reading circuit for reading data from the selected address in said memory array;
• an expected value register for storing an expected value of read data from the selected address in said memory array;
• and
• a determining circuit for determining whether a failure occurs in the memory cell at the selected address in accordance with output data of said reading circuit, data stored in said expected value register, said selected address, and a failure mode instruction signal and outputting a signal indicative of a result of determination, said failure mode instructing signal designating whether a failure to be detected is a change from high-level data to low-level data of memory cell data or a change from the low-level data to the high-level data of the memory cell data.