Semiconductor memory device
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsJunko Matsumoto, Tadaaki Yamauchi, Takeo Okamoto
Life of this patent
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Abstract
For a memory array, a main data bus commonly used for first and second data bit widths, and a main data bus used only for the second data bit width are disposed. According to a data bit width, connection between memory blocks and main data lines is switched. The main data buses are connected to write/read circuits, and expanding/compressing operation on data bits is performed by an expansion/compression circuit in a unit of a predetermined number of bits. Thus, with the same configuration irrespective of data bit width, compression of data bits in the multi-bit test can be performed to output the compression result to the same data terminal.
Claims12
A semiconductor memory device having a data bit width settable selectively to a first bit width and a second bit width wider than said first bit width, comprising:
- first data terminals of the first bit width used in both of a mode of said first bit width and a mode of said second bit width;
- first main data lines, having said first bit width, disposed corresponding to said first data terminals, a correspondence relationship between said first main data lines and said first data terminals being the same between the mode of said first bit width and the mode of said second bit width;
- one or more second data terminals, non-used in the mode of said first bit width, having a bit width equal to a difference between the first and second bit widths;
- and
- one or more second main data lines, disposed corresponding to said one or more second data terminals, having a bit width equal to a bit width of said one or more second data terminals.
Dependencies are inferred from the claim text.