Semiconductor storage device and setting method thereof
AssigneeKabushiki Kaisha Toshiba
InventorsMasatsugu Kojima, Tomoharu Tanaka, Noboru Shibata
Life of this patent
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Abstract
A semiconductor storage device includes a main memory cell array and a redundancy memory cell array. The redundancy memory cell array is set to selectively have a replacing area replacing a defective memory cell in the main memory cell array, and a non-replacing area other than the replacing area. Memory cells in the main memory cell array and the redundancy memory cell array are selected and driven by a memory selection circuit. A control section for controlling the memory selection circuit is set to assign main memory addresses to memory cells in the non-replacing area, and use these memory cells as an expansion area of the main memory cell array.
Claims22
A semiconductor storage device comprising:
- a main memory cell array including a plurality of memory cells;
- a redundancy memory cell array including a plurality of memory cells, which are usable to replace a defective memory cell in the main memory cell array, the redundancy memory cell array being set to selectively have a replacing area replacing a defective memory cell in the main memory cell array, and a non-replacing area other than the replacing area;
- a memory selection circuit configured to select and drive memory cells in the main memory cell array and the redundancy memory cell array;
- a control section configured to control the memory selection circuit, the control section being set to assign main memory addresses to memory cells in the non-replacing area, and use these memory cells as an expansion area of the main memory cell array.
A semiconductor storage device comprising:
- a main memory cell array including a plurality of memory cells;
- a redundancy memory cell array including a plurality of memory cells, which are usable to replace a defective memory cell in the main memory cell array;
- a memory selection circuit configured to select and drive memory cells in the main memory cell array and the redundancy memory cell array, the memory selection circuit including a replacing circuit portion configured to replace a defective memory cell in the main memory cell array with a memory cell in the redundancy memory cell array, and the redundancy memory cell array being set by the replacing circuit portion to selectively have a replacing area replacing a defective memory cell in the main memory cell array, and a non-replacing area other than the replacing area;
- an address increment circuit configured to supply the memory selection circuit with an address signal having address numbers gradually increased from a main memory address, so as to access memory cells in the non-replacing area, in succession to memory cells in the main memory cell array;
- and
- an end address control circuit configured to generate an end signal indicating that a selected specific address in the non-replacing area is an end address, wherein the address increment circuit stops operating upon the end signal being present.
A method of setting a semiconductor storage device, comprising:
- setting a redundancy memory cell array to selectively have a replacing area replacing a defective memory cell in a main memory cell array, and a non-replacing area other than the replacing area;
- and
- setting a control section to assign main memory addresses to memory cells in the non-replacing area, and use these memory cells as an expansion area of the main memory cell array, wherein the control section controls the memory selection circuit configured to select and drive memory cells in the main memory cell array and the redundancy memory cell array.
Dependencies are inferred from the claim text.