Integrated semiconductor memory having memory cells in a plurality of memory cell arrays and method for repairing such a memory

A method for repairing an integrated semiconductor memory, which comprises:

• providing memory cells disposed in a plurality of memory cell arrays;
• providing a semiconductor chip on which the memory cell arrays are disposed in levels extended above one another;
• providing the memory cells with a plurality of memory cells combined to form addressable normal units of memory cells;
• providing the memory cells with a plurality of memory cells combined to form redundant units of memory cells each for jointly replacing a respective one of the normal units;
• providing each of the normal units and the redundant units with memory cells of the memory cell arrays in a plurality of the levels;
• testing the memory cells in the memory cell arrays for freedom from fault;
• replacing memory cells detected as faulty with redundant memory cells;
• and
• replacing a respective normal unit containing a memory cell detected as faulty with one of the redundant units, upon detecting at least one faulty memory cell.