Semiconductor memory and memory board therewith
AssigneesNEC Corporation, NEC Electronics Corporation
InventorDaiki Nakajima
Life of this patent
Estimating the term…
Abstract
A semiconductor memory, enabled to be used efficiently, if defective is provided. The semiconductor memory (100) may include a first memory blocks (3), a second memory block (33) a shutoff signal generation circuit (1), and a switch circuit (2). The shutoff signal generation circuit (1) may include a programmable device (12) that indicates if the memory block (3) is defective. External terminals (DQ0 to DQ7) may be connected to the memory block (3) through the switch circuit (2) when there is no defect and may be disconnected from the memory block (3) when there is a defect.
Claims22
A semiconductor memory, comprising:
- a first memory;
- external terminals;
- a shutoff circuit that disrupts an electrical connection between the external terminals and the first memory when the first memory is defective;
- and
- a second memory formed integrally with the first memory that is not accessed by the external terminals.
A semiconductor memory, comprising:
- a first memory block;
- a first switch circuit coupled between first external terminals and the first memory block;
- a second memory block formed integrally with the first memory block;
- a first shutoff signal generating circuit including a first programmable device wherein the first shutoff signal generation circuit outputs a first shutoff signal coupled to the first switch circuit and the first switch circuit electrically disconnects the first memory block from the first external terminals in response to the first shutoff signal;
- a second switch circuit coupled between second external terminals and the second memory block, the second external terminals being different than the first external terminals;
- and
- a second shutoff signal generating circuit including a second programmable device wherein the second shutoff signal generation circuit outputs a second shutoff signal coupled to the second switch circuit and the second switch circuit electrically disconnects the second memory block from the second external terminals in response to the second shutoff signal.
A method for inspecting a semiconductor memory including a first and second memory integrally formed, external terminals, a shutoff circuit including a programmable device wherein the shutoff circuit electrically disconnects the external terminals from the first memory when the first memory is defective, comprising the steps of:
- inspecting whether or not the first memory is defective;
- and
- setting the programmable device in a first state depending on whether or not the first memory is defective to alter the electrical connection between first external terminals from the first memory, wherein the first external terminals do not provide access to the second memory.
Dependencies are inferred from the claim text.