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US 6,650,575 B1Granted
Programmable delay circuit within a content addressable memory
AssigneeNetLogic Microsystems, Inc.
InventorSandeep Khanna
Life of this patent
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Abstract
An apparatus having an output register coupled to a content addressable memory (CAM) array. The output register may be configured to output data based on a delayed clock signal. A programmable delay circuit may be coupled to receive a reference clock signal and generate the delayed clock signal using one or more delay elements.
Claims11
An integrated circuit device configured to operate based on a reference clock signal, comprising:
- a clock pad to receive the reference clock signal;
- a programmable delay circuit coupled to receive the reference clock signal and generate a delayed clock signal using at least one delay element, wherein the programmable delay circuit comprises:
- a plurality of the delay elements to generate a plurality of delayed clock signals;
- a programmable register to store information indicating a particular delayed clock signal of the plurality of delayed clock signals;
- and
- a multiplexer coupled with the programmable register and the plurality of delay elements to select the particular delayed clock signal based on the information;
- an output register configured to output data based on the delayed clock signal;
- and
- a second programmable delay circuit coupled between the programmable delay circuit and the output register.
6 more elements
An integrated circuit device configured to operate based on a reference clock signal, comprising:
- a clock pad to receive the reference clock signal;
- a programmable delay circuit coupled to receive the reference clock signal and generate a delayed clock signal using at least one delay element, wherein the programmable delay circuit comprises:
- a plurality of the delay elements to generate a plurality of delayed clock signals;
- a programmable register to store information indicating a particular delayed clock signal of the plurality of delayed clock signals, wherein the information for the programmable register indicates the particular delayed clock signal according to a frequency of the reference clock signal;
- and
- a multiplexer coupled with the programmable register and the plurality of delay elements to select the particular delayed clock signal based on the information;
- an output register configured to output data based on the delayed clock signal.
4 more elements
A method, comprising:
- receiving a reference clock signal;
- generating a delayed clock signal based on the reference clock signal using programmed information representing a value of a delay time period;
- and
- outputting data based on the delayed clock signal, wherein the reference clock signal is received by a content addressable memory (CAM) device and the delayed clock signal is generated internally in the CAM device.
1 more element
A method, comprising:
- receiving a reference clock signal;
- generating a delayed clock signal based on the reference clock signal using programmed information representing a value of a delay time period;
- outputting data based on the delayed clock signal;
- and
- generating the delayed clock signal using a second programmed information representing the value of second delay time period.
2 more elements
An apparatus, comprising:
- means for receiving a reference clock signal;
- means for generating a delayed clock signal based on the reference clock signal using programmed information representing a value of a delay time period;
- means for outputting data based on the delayed clock signal;
- and
- means for generating the delayed clock signal using additional programmed information representing the value of second delay time period.
2 more elements
Dependencies are inferred from the claim text.