Semiconductor device preventing signal delay among wirings

A semiconductor device comprising:

• a first memory cell array having a plurality of memory cells;
• a second memory cell array having a plurality of memory cells;
• a plurality of first wirings arranged approximately in parallel, the first wirings propagating an address signal for selecting a memory cell of the first and second memory cell arrays;
• a first decoder connected between the first memory cell array and the first wirings, the first decoder decoding the address signal propagated in the first wirings;
• a second decoder connected between the second memory cell array and first wirings, the second decoder decoding the address signal propagated in the first wirings;
• a first amplifier arranged at one of the first two adjacent wirings included in the first wirings, the first amplifier being arranged at least at a position which divides the interval of a predetermined distance of one of the first wirings by approximately 1/n, n being an integer of two or more, and being constituted by an odd number of inverter circuits;
• a first driver provided in the other first wiring of the adjacent two first wirings, the first driver driving the other first wiring;
• a second driver provided in the first one wiring, the second driver having a current drive capacity of 1/n of the first driver which drives the first one wiring;
• and
• wherein the first amplifier has a current drive capacity of at least 1/n of the first driver.

A semiconductor device comprising:

• a first memory cell array having a plurality of memory cells;
• a second memory cell array having a plurality of memory cells;
• a first data line arranged corresponding to the first and second memory cell arrays;
• a second data line arranged approximately in parallel to the first data line;
• a first switch which connects the first data line to the first memory cell array;
• a second switch which connects the first data line to the second memory cell array;
• a third switch which connects the second data line to the first memory cell array;
• a fourth switch which connects the second data line to the second memory cell array;
• and
• an amplifier arranged at least at a position which divides the interval of a predetermined distance of the second data line by approximate in 1/n, n being an integer of two or more, the amplifier being constituted by an odd number of inverter circuits,
• wherein the first and third switches are connected to the input side of the amplifier, and the second and fourth switches are connected to the output side of the amplifier.

A semiconductor device comprising:

• a plurality of memory macros arranged on a semiconductor chip, each memory macro having a memory cell array;
• a first address wiring shared by a plurality of memory macros;
• a second address wiring arranged approximately in parallel to the first address line;
• a first amplifier arranged at least at a position which divides the interval of a predetermined distance of the first address wiring by approximately 1/n, n being an integer of two or more, the first amplifier being constituted by an odd number of inverter circuits;
• and
• a second amplifier arranged at least at a position which divides the interval of a predetermined distance of second address wiring by approximately 1/n, the second amplifier being constituted by an even number of inverter circuits.