Non-volatile semiconductor memory

A non-volatile semiconductor memory device comprising:

• a memory cell array having a plurality of non-volatile memory cells;
• word lines, bit lines and source lines connected to said memory cells;
• a row decoder configured to select one of said word lines;
• a column decoder configured to select one of said bit lines;
• at least one reference cell;
• a read circuit configured to read data by applying a first voltage to said one of said word lines to compare a current flowing through said one of said bit lines with a current flowing through said reference cell;
• a program circuit configured to program said data by applying a voltage to at least two selected from said word lines, said bit lines, said source lines and a semiconductor region including said memory cells;
• first and second regulators;
• and
• a program verify circuit configured to detect whether programming has finished by applying an output voltage of said second regulator to said word lines of said memory cells to be programmed, while applying an output voltage of said second regulator to a word line of said reference cell, thereby comparing a cell current of selected one of said memory cells with a cell current of said reference cell.

A non-volatile semiconductor memory device comprising:

• a memory cell array having a plurality of non-volatile memory cells each having three or more threshold voltage levels;
• word lines, bit lines and source lines connected to said memory cells;
• a row decoder configured to select one of said word lines;
• a column decoder configured to select one of said bit lines;
• first and second reference cells;
• first, second and third load current sources;
• a first load circuit configured to provide a first voltage output from both a first load current and a current flowing through said one of said bit lines by applying a first word line voltage to said one of said word lines;
• a second load circuit configured to provide a second voltage output from both a second load current and a current flowing through said one of said bit lines by applying said first word line voltage to a word line of said first reference cells;
• a first read circuit configured to decide whether said memory cells are at one of first and second levels by comparing said first voltage output with said second voltage output;
• a third load circuit configured to provide a third voltage output front both a third load current and a current flowing through said one of said bit lines by applying said first word line voltage to a word line of said second reference cells;
• and
• a second read circuit configured to decide whether said memory cells are at one of second and third levels by comparing said second voltage output with said third voltage output,
• wherein N1/N2 is larger than I1/I2 where N1 (N1≧1, positive integer) is the number of said first reference cells connected in parallel with one another, N2 (N2≧1, positive integer) is the number of said second reference cells connected in parallel with one another, I1 is said second load current and I2 is said third load current.

A non-volatile semiconductor memory device comprising:

• a memory cell array having first and second non-volatile memory cells each having three or more threshold voltage levels;
• word lines, bit lines and source lines connected to said memory cells;
• a row decoder configured to select one of said word lines;
• a column decoder configured to select one of said bit lines;
• first to fourth reference cells;
• first to sixth load current sources;
• and
• first to third comparators,
• wherein when a first mode signal is a first logic, said first memory cell and said first load current source are provided as a first input of said first comparator, said second memory cell and said second load current source are provided as a first input of said second comparator, and said first reference cell and said third load current source are provided as a common second input of said first and second comparators, so that said third comparator is set to an inactivated condition, respectively, and
• wherein when said first mode signal is a second logic, one of said first and second memory cells is connected to one of said first and second load current sources, so that the connection node is provided as a first input of said first to third comparators, said second reference cell and said fourth load current source are provided as a second input of said first comparator, said third reference cell and said fifth load current source are provided as a second input of said second comparator, and said fifth reference cell and said sixth load current source are provided as a second input of said third comparator, respectively.

A non-volatile semiconductor memory device comprising:

• a memory cell array having a plurality of non-volatile memory cells;
• word lines, bit lines and source lines connected to said memory cells;
• a row decoder configured to select one of said word lines;
• a column decoder configured to select one of said bit lines;
• at least one reference cell;
• and
• a comparator circuit configured to compare a cell current of said reference cell with a cell current of selected one of memory cells,
• wherein a first input of said comparator circuit is connected to said selected one of said memory cells when a first signal is a first logic, while said first input is connected to one of current sources selected from internal and external current sources when said first signal is a second logic, and
• wherein a threshold voltage of said reference cell is controlled while monitoring an output voltage of said comparator circuit when said first signal is said second logic.

A non-volatile semiconductor memory device comprising:

• a memory cell array having a plurality of non-volatile memory cells each having three or more threshold voltage levels;
• word lines, bit lines and source lines connected to said memory cells;
• a row decoder configured to select one of said word lines;
• a column decoder configured to select one of said bit lines;
• at least one reference cell;
• a read circuit configured to read data of said memory cells by applying a first voltage to said word lines to compare a current flowing through said bit lines with a current flowing through said reference cell;
• an erase circuit configured to erase data of said memory cells by applying a voltage to at least one selected from said word lines, bit lines, source lines, and a semiconductor region including said memory cells;
• and
• an erase verify circuit configured to compare a cell current of a selected memory cell with a cell current of said reference cell by applying said first voltage to said memory cells to be erased while applying a second voltage different from said first voltage to a word line of said reference cell.

A non-volatile semiconductor memory device comprising:

• a memory cell array having a plurality of non-volatile memory cells each having three or more threshold voltage levels;
• word lines, bit lines and source lines connected to said memory cells;
• a row decoder configured to select one of said word lines;
• a column decoder configured to select one of said bit lines;
• at least one reference cell;
• a read circuit configured to read data of said memory cells by applying a first voltage to said word lines to compare a current flowing through said bit lines with a current flowing through said reference cell;
• a program circuit configured to program data to said memory cells by applying a voltage to at least one selected from said word lines, bit lines, source lines, and a semiconductor region including said memory cells;
• and
• a program verify circuit configured to compare a cell current of a selected memory cell with a cell current of said reference cell by applying said first voltage to said memory cells to be programmed while applying a second voltage different from said first voltage to a word line of said reference cell.